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| Patent # | Description |
|---|---|
| US-9,554,039 |
All-in-focus implementation Various systems and methods for an all-in-focus implementation are described herein. A system to for operating a camera, comprising an image sensor in the... |
| US-9,553,960 |
Loudspeaker with laminate panel for mobile computing platforms Systems and methods enhancing loudspeaker audio performance in thin devices, such as mobile computing platforms and/or communication handsets. In some... |
| US-9,553,853 |
Techniques for load balancing in a packet distribution system Various embodiments are generally directed to techniques to distribute encrypted packets among multiple cores in a load-balanced manner for further processing.... |
| US-9,553,643 |
User equipment and methods for codebook subsampling for enhanced 4TX
codebooks Embodiments of user equipment (UE) and methods for codebook subsampling for enhanced 4TX codebooks in 3GPP LTE wireless networks are generally described herein.... |
| US-9,553,637 |
Near field communications (NFC) and proximity sensor for portable devices Described herein are techniques related to near field coupling and proximity sensing operations. For example, a proximity sensor uses a coil antenna that is... |
| US-9,553,519 |
Small form factor voltage adapters and devices, platforms, and techniques
for managing power boosts Techniques and devices related to power adapters for mobile devices and, in particular, small form factor power adapters that allow a voltage droop during a... |
| US-9,553,352 |
Communication device and display incorporating antennas between display
pixels A display, such as for a touch-sensitive communication device, can include a transparent cover glass, pixels that emit light through the cover glass, and... |
| US-9,553,099 |
Pillar arrangement in NAND memory Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the... |
| US-9,553,075 |
Recessed and embedded die coreless package Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a... |
| US-9,553,018 |
Self-aligned via and plug patterning with photobuckets for back end of
line (BEOL) interconnects Self-aligned via and plug patterning with photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an... |
| US-9,552,995 |
Electrical interconnect for an electronic package Some example forms relate to an electrical interconnect for an electronic package. The electrical interconnect includes a dielectric layer that includes a... |
| US-9,552,977 |
Landside stiffening capacitors to enable ultrathin and other low-Z
products Embodiments of systems, devices, and methods to minimize warping of ultrathin IC packaged products are generally described herein. In some embodiments, an... |
| US-9,552,854 |
Register files including distributed capacitor circuit blocks Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second... |
| US-9,552,781 |
Content adaptive LCD backlight control An apparatus, computing device, and a computer readable medium are described herein. The apparatus includes logic to process pixels using content adaptive LCD... |
| US-9,552,620 |
Depth offset compression Zmin and Zmax are determined for depth offset compression. Then a check determines whether Zmin is equal to Zmax. If so, only one of Zmin and Zmax is used for... |
| US-9,552,500 |
Always-available embedded theft reaction subsystem A platform including an always-available theft protection system is described. In one embodiment, the system comprises an arming logic to arm the platform, when... |
| US-9,552,316 |
Techniques for adaptive interface support Techniques for adaptive interface support are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of which is in... |
| US-9,552,313 |
Delivering real time interrupts with an advanced programmable interrupt
controller Embodiments of apparatuses and methods for delivering real time interrupts with an APIC are disclosed. In one embodiment, an apparatus includes a local advanced... |
| US-9,552,308 |
Early wake-warn for clock gating control A request associated with a particular cache record is generated to be sent to a system component associated with a cache bank over an interconnect. A wake-warn... |
| US-9,552,303 |
Method and system for maintaining release consistency in shared memory
programming A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in... |
| US-9,552,269 |
Test logic for a serial interconnect An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages,... |
| US-9,552,267 |
SATA receiver equalization margin determination/setting method and
apparatus Apparatuses, methods and storage medium associated with automatic SATA receiver equalization margin determination and setting, are disclosed. In embodiments, an... |
| US-9,552,253 |
Probabilistic flit error checking A bit error in a flit transmitted over a link is determined to affect one or more particular bits of the flit based on a syndrome value associated with a cyclic... |
| US-9,552,209 |
Functional unit for instruction execution pipeline capable of shifting
different chunks of a packed data... A method is described that includes fetching an instruction. The method further includes decoding the instruction. The instruction specifies an operation, a... |
| US-9,552,207 |
Method and apparatus for performance efficient ISA virtualization using
dynamic partial binary translation Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native... |
| US-9,552,205 |
Vector indexed memory access plus arithmetic and/or logical operation
processors, methods, systems, and... A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is... |
| US-9,552,169 |
Apparatus and method for efficient memory renaming prediction using
virtual registers A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a... |
| US-9,552,164 |
Apparatus, method and system for determining reference voltages for a
memory Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an... |
| US-9,552,159 |
Configuration information backup in memory systems According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status... |
| US-9,552,051 |
Block partition to minimize power leakage Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal... |
| US-9,552,045 |
Method, apparatus, and system for controlling power consumption of unused
hardware of a link interface In an embodiment, a plurality of hardware buffers each may store information associated with one or more virtual channels. In turn, a configuration logic is to... |
| US-9,552,039 |
Constrained boot techniques in multi-core platforms Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that... |
| US-9,551,916 |
Integrated and adjustable image projection with auto-image correction in
electronic devices using an in-facing... A system and method for implementing integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or... |
| US-9,551,741 |
Current tests for I/O interface connectors Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data... |
| US-9,551,682 |
High throughput biochemical detection using single molecule fingerprinting
arrays Various embodiments provide devices, methods, and systems for high throughput biomolecule detection using transducer arrays. In one embodiment, a transducer... |
| US-9,551,352 |
Techniques for improved volumetric resistance blower apparatus, system and
method Embodiments of an apparatus, system, method and techniques are described for an improved volumetric resistance blower and rotor. An apparatus may comprise, for... |
| US-9,551,177 |
Rotational to translational locking hinge Techniques related to a hinge in a computing device are described herein. The techniques may include forming a shaft to move rotationally, and forming a sliding... |
| US-9,550,670 |
Stress buffer layer for integrated microelectromechanical systems (MEMS) Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first... |
| US-9,550,495 |
Technologies for assisting vehicles with changing road conditions Technologies for assisting vehicles with changing road conditions includes vehicle assistance data based on crowd-sourced road data received from a plurality of... |
| US-9,549,421 |
Network coverage hole detection A technology for a user equipment (UE) that is operable to connect to a third generation partnership project (3GPP) long term evolution (LTE) cell in a cellular... |
| US-9,549,404 |
Blind decoding for an enhanced physical downlink control channel (EPDCCH) Technology for a user equipment (UE) configured for blind decoding downlink control information (DCI) from an enhanced physical downlink control channel... |
| US-9,549,378 |
Power loading in MU-MIMO Embodiments of a system and method for transmitting data from an access point in a multiple user multiple input multiple output (MU-MIMO) system are provided. A... |
| US-9,549,286 |
Geo-fence notification management Embodiments for geo-fence notification management are generally described herein. A mobile device for geo-fence notification management may include a... |
| US-9,549,280 |
Wireless data transfer with improved transport mechanism selection Generally, this disclosure describes devices, systems and methods for wireless data transfer with improved transport mechanism selection. The device may include... |
| US-9,549,254 |
Method and system of acoustic signal mixing A system, article, and method of acoustic signal mixing comprises use of a total pair that is a count of the number of addition coefficients and subtraction... |
| US-9,549,188 |
Golden frame selection in video coding Techniques related to designating golden frames and to determining frame sizes and/or quantization parameters golden and non-golden frames for video coding are... |
| US-9,548,986 |
Sensitive data tracking using dynamic taint analysis A system and method for tracking sensitive data uses dynamic taint analysis to track sensitive data as the data flows through a target application running on a... |
| US-9,548,937 |
Backpressure techniques for multi-stream CAS Techniques are disclosed for controlling data transmission in multi-stream digital systems. The techniques disclosed allow an input stream to a conditional... |
| US-9,548,879 |
Virtual multicarrier design for orthogonal frequency division multiple
access communications Embodiments of the present invention provide a virtual multicarrier design for orthogonal frequency division multiple access communications. Other embodiments... |
| US-9,548,815 |
Apparatus for visible light communications in accordance with UFSOOK and
FSK dimming Embodiments may provide a way of communicating via an electromagnetic radiator, or light source, that can be amplitude modulated such as light emitting diode... |
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