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Semiconductor devices with germanium-rich active layers and doped
Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped...
Antifuse element utilizing non-planar topology
Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements...
Package on wide I/O silicon
An apparatus including a die including a device side and an opposite backside, first contacts on the backside and a through vias from the device side to the...
Tall solders for through-mold interconnect
Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. A package can include a chip...
Microelectronic package and stacked microelectronic assembly and computing
system containing same
A microelectronic package comprises a die (110, 210) and a plurality of electrically conductive layers (120, 220) and electrically insulating layers (130, 230),...
Apparatus and method to monitor die edge defects
Described is an apparatus comprising: an input pad; an output pad; a wire, coupled to the input pad and the output pad, the wire positioned at a periphery of a...
Replacement metal gates to enhance transistor strain
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
Thermally and electrically conductive structure comprising a carbon
nanotube, a graphite sheet and a metal...
A thermally and electrically conductive structure comprises a carbon nanotube (110) having an outer surface (111) and a carbon coating (120) covering at least a...
Systems, methods, and computer program products for low-latency warping of
a depth map
Methods, systems, and computer program products to warp a depth map into alignment with an image, where the image sensor (e.g., camera) responsible for the...
Securing display output data against malicious software attacks
Systems, apparatus and methods are described including operations for securing display output data against malicious software attacks.
System and method for out-of-band assisted biometric secure boot
In some embodiments, the invention involves using a dedicated service processor with out-of-band capabilities to enable a secure boot using biometric data to...
Unauthorized access and/or instruction prevention, detection, and/or
remediation, at least in part, by storage...
An embodiment may include a storage processor that may be comprised, at least in part, in a host. The host may include at least one host central processing unit...
Software modification for partial secure memory processing
This disclosure is directed to software modification that may be used to prevent software piracy and prevent unauthorized modification of applications. In some...
Page coloring with color inheritance for memory pages
Apparatuses, methods, and media for page coloring with color inheritance for memory pages are disclosed. Some embodiments may include an interface to access a...
Stride-based translation lookaside buffer (TLB) prefetching with adaptive
A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the...
Linear to physical address translation with support for page attributes
Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page...
Apparatus and method for implementing a scratchpad memory using priority
An apparatus and method for implementing a scratchpad memory within a cache using priority hints. For example, a method according to one embodiment comprises:...
Hiding instruction cache miss latency by running tag lookups ahead of the
This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the...
Dynamically controlling cache size to maximize energy efficiency
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a...
On chip redundancy repair for memory devices
An apparatus, system, and method provide for on chip redundancy repair for stacked memory devices. A memory device may include a memory stack including one or...
Method and system for error management in a memory device
A method and system for error management in a memory device. In one embodiment of the invention, the memory device can handle commands and address parity errors...
Optimizing fixed point divide
Systems, apparatus and methods are described related to optimizing fixed point divide.
A method and system for a software driver of a graphics controller to work with a display codec. The software driver may be configured to work with different...
Power management for a system on a chip (SoC)
In one embodiment, the present invention includes a method for sending a first link handshake signal between a first subsystem and a power management unit (PMU)...
System and method for conveying service latency requirements for devices
connected to low power input/output...
In at least one embodiment described herein, an apparatus is provided that can include means for communicating a latency tolerance value for a device connected...
Dynamic power limit sharing in a platform
A method and apparatus for dynamic power limit sharing among the modules in the platform. In one embodiment of the invention, the platform comprises a processor...
Mechanism for proximity detection based on Wi-Fi signals
A mechanism is described for proximity detection based on Wi-Fi signals. A method of embodiments of the invention includes determining strength of one or more...
Methods and arrangements for beam refinement in a wireless network
In some embodiments a beamforming method is disclosed. The method can include transmitting a beam having a channel defined by a maximum ratio transmission...
Delivery edge profile aggregation
A system and method for aggregating subscriber information at a delivery edge is disclosed. The method comprises interfacing a user profile aggregation device...
Interference mitigation in the context of heterogeneous networks with
coordinated transmission points with a...
Technology is discussed for extending frequency and time based approaches, such as Inter-Cell Interference Coordination (ICIC) and enhanced ICIC (eICIC), to...
Optimizing semi-active workloads
Devices and methods for optimizing semi-active workloads are described herein. A network interface device may be configured to offload data packet...
Coverage adjustment in E-UTRA networks
Embodiments of systems and techniques for coverage adjustment in evolved universal terrain radio access networks (E-UTRANs) are described. In some embodiments,...
Systems and methods for securing near field communications
Systems and methods to secure near field communications (NFC) are disclosed. An NFC polling device may detect a change in voltage when attempting to communicate...
Concurrent linked-list traversal for real-time hash processing in
multi-core, multi-thread network processors
Described embodiments process hash operation requests of a network processor. A hash processor determines a job identifier, a corresponding hash table, and a...
Network based data traffic detection and control
A network-based apparatus for imposing a minimum transmit latency on data packets of a prescribed data type on a network includes at least one processor. The...
Uplink coordinated multi-point
Disclosed embodiments may include an apparatus having one or more processors coupled to one or more computer-readable storage media. The one or more processors...
Sounding reference signal (SRS) mechanism for intracell device-to-device
Technology for device discovery using a device-to-device (D2D) sounding reference signal (SRS) and device discovery using D2D SRS in a channel measurement group...
Device, system and method of wireless communication between circuits
Some demonstrative embodiments include devices, systems and/or methods of wireless communication between circuits. For example, an integrated chip may include a...
Signaling for downlink coordinated multipoint in a wireless communication
Embodiments herein describe apparatuses, systems, and methods for signaling to support downlink coordinated multipoint (CoMP) communications with a user...
Adaptation techniques in MIMO
A method of the multiple input multiple output feedback is disclosed. In accordance with an embodiment of the invention, the multiple input multiple output...
Fractional symbol based phase noise mitigation
Fractional symbol based phase noise mitigation, including methods and systems to determine phase noise trajectory, or indication of phase noise, for each of...
Signal peak-to-average power ratio (PAR) reduction
A method of reducing a peak to average power ratio (PAR) of a signal may include generating an in-band error signal indicating in-band distortion of a...
Search unit to accelerate variable length compression/decompression
Systems and methods to accelerate compression and decompression with a search unit implemented in the processor core. According to an embodiment, a search unit...
Device, system and method of wireless communication over a plurality of
wireless communication frequency channels
Some demonstrative embodiments include devices, systems and/or methods of wireless communication over a plurality of wireless communication frequency channels....
Bridge driver for a switching voltage regulator which is operable to
soft-switch and hard-switch
Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to...
Techniques for forming non-planar germanium quantum well devices
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV...
III-V layers for N-type and P-type MOS source-drain contacts
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example...
Bumpless build-up layer package including an integrated heat spreader
An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die...
Integrated inductor structure and method of fabrication
An inductor structure comprised of a magnetic section and a single turn solenoid. The single turn solenoid to contain within a portion of the magnetic section...