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Patent # Description
US-9,143,155 RF DAC with configurable DAC mixer interface and configurable mixer
One embodiment of the present disclosure relates to a circuit. The circuit includes a digital to analog converter (DAC) configured to convert a time-varying,...
US-9,143,120 Mechanisms for clock gating
Mechanisms for clock gating. A clock generation circuit provides a clock signal over a clock signal distribution network within an integrated circuit package....
US-9,142,510 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal...
A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed...
US-9,142,482 Transient thermal management systems for semiconductor devices
Thermal management systems for semiconductor devices are provided. Embodiments of the invention provide two or more liquid cooling subsystems that are each...
US-9,142,480 Microelectronic package with high temperature thermal interface material
A microelectronic package is provided. The microelectronic package includes a substrate, a die coupled to a top surface of the substrate and a integrated heat...
US-9,142,475 Magnetic contacts
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with magnetic contacts, as well as corresponding fabrication...
US-9,142,421 Double patterning lithography techniques
Techniques are disclosed for double patterning of a lithographic feature using a barrier layer between the pattern layers. In some cases, the techniques may be...
US-9,142,347 Semiconductor package with air core inductor (ACI) having a metal-density layer unit of fractal geometry
Semiconductor packages with air core inductors (ACIs) having metal-density layer units of fractal geometry are described. In an example, an inductor structure...
US-9,142,271 Reference architecture in a cross-point memory
The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a...
US-9,142,192 Simulation of web applications and secondary devices in a web browser, web application development tools, and...
Device simulators and methods for using the same are disclosed. In some embodiments, the device simulators are capable of permitting accurate pixel to pixel and...
US-9,142,167 Thin-film transitor backplane for displays
An electro-optical element may be controlled by a circuit. The circuit may include two transistors having a control capacitor coupled to the common node of the...
US-9,142,022 3D object tracking
Embodiments relate to tracking a pose of a 3D object. In embodiments, a 3D computer model, consisting of geometry and joints, matching the 3D real-world object...
US-9,142,008 Hierarchical motion blur rasterization
Motion blur rasterization may involve executing a first test for each plane of a tile frustum. The first test is a frustum plane versus moving bounding box...
US-9,142,001 Performance allocation method and apparatus
In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for...
US-9,141,975 Inferring user risk profile from travel patterns
A method for estimating a risk profile of a user of a personal digital assistant (PDA) includes collecting, using the PDA, data indicative of a travel pattern...
US-9,141,946 Dynamic payment service
Systems and methods may provide for implementing a dynamic payment service. In one example, the method may generate a request communication including purchase...
US-9,141,855 Accelerated object detection filter using a video motion estimation module
Systems, apparatus and methods are described related to accelerated object detection filter using a video estimation module.
US-9,141,848 Automatic media distribution
In accordance with some embodiments, wireless devices may automatically form ad hoc networks to enable more efficient sharing of media between the devices and...
US-9,141,802 Computing device boot software authentication
Various embodiments are generally directed to authenticating a chain of components of boot software of a computing device. An apparatus comprises a processor...
US-9,141,586 Method, apparatus, system for single-path floating-point rounding flow that supports generation of...
A mechanism for performing single-path floating-point rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a...
US-9,141,577 Optimized link training and management mechanism
In one embodiment, a converged protocol stack can be used to unify communications from a first communication protocol to a second communication protocol to...
US-9,141,573 Power-optimized interrupt delivery
An apparatus, method, system, and computer-readable medium are disclosed. In one embodiment the apparatus is a processor. The processor includes thread...
US-9,141,570 Enabling virtualization of a processor resource
In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with...
US-9,141,560 Multi-level storage apparatus
A multi-level storage apparatus includes a first-level storage area to store first information, a second-level storage area to store second information, and a...
US-9,141,559 Increasing virtual-memory efficiencies
Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which...
US-9,141,555 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-9,141,536 Nonvolatile memory wear management
Embodiments describe methods, apparatus, and system configurations for providing targeted wear management in nonvolatile memory. Specifically, embodiments may...
US-9,141,469 Efficient and scalable cyclic redundancy check circuit using Galois-field arithmetic
Embodiments of the present disclosure describe methods, apparatus, and system configurations for cyclic redundancy check circuits using Galois-field arithmetic.
US-9,141,466 Correcting double-bit burst errors using a low density parity check technique
Embodiments of systems, apparatuses, and methods for correcting double bit burst errors using a low density parity check technique are disclosed. In one...
US-9,141,461 Machine check architecture execution environment for non-microcoded processor
A technology for implementing a method for a machine check architecture environment. A method of the disclosure includes obtaining an occurrence of an error....
US-9,141,454 Signaling software recoverable errors
Embodiments of an invention for signaling software recoverable errors are disclosed. In one embodiment, a processor includes a first unit, a programmable...
US-9,141,426 Processor having per core and package level P0 determination functionality
A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first...
US-9,141,387 Processor executing unpack and pack instructions specifying two source packed data operands and saturation
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source...
US-9,141,386 Vector logical reduction operation implemented using swizzling on a semiconductor chip
A semiconductor processor is described. The semiconductor processor includes logic circuitry to perform a logical reduction instruction. The logic circuitry has...
US-9,141,362 Method and apparatus to schedule store instructions across atomic regions in binary translation
A method and system to support scheduling of memory store instructions across atomic regions in binary translation in a processing unit or processor. In one...
US-9,141,361 Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation
Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native...
US-9,141,299 Method for reducing power consumption in solid-state storage device
Apparatus and methods of reducing power consumption in solid-state storage devices such as solid-state disks (SSDs) that can reduce idle power levels in an SSD,...
US-9,141,199 Intelligent graphics interface in a handheld wireless device
Various embodiments of the invention may allow applications and information to be clustered together in ways that simplify and automate various tasks. Other...
US-9,141,180 Method and apparatus for a zero voltage processor sleep state
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A...
US-9,141,179 Fine grained power management in virtualized mobile platforms
A system and method of managing power may include determining a power state based on a first power management request from a first operating system executing on...
US-9,141,171 Network routing protocol power saving method for network elements
Methods and apparatus relating to network routing protocols to support power savings in network elements. A most utilized link path network topology for a...
US-9,141,170 Techniques to control self refresh display functionality
Techniques are described to monitor a level of graphics processing activity and control power usage based on the level. When no graphics processing activity is...
US-9,141,167 Apparatus and method to manage energy usage of a processor
In an embodiment, a processor includes at least one processor core and power control logic having energy usage logic to predict an energy usage of the processor...
US-9,141,166 Method, apparatus, and system for energy efficiency and energy conservation including dynamic control of energy...
An apparatus, method and system is described herein for dynamic power control of a power domain. A power limit over a time window is provided. And over a...
US-9,141,162 Apparatus, system and method for gated power delivery to an I/O interface
Techniques and mechanisms for managing a delivery of power to a resource of an input/output (I/O) interface. In an embodiment, a first link of a plurality of...
US-9,141,134 Utilization of temporal and spatial parameters to enhance the writing capability of an electronic device
The enhanced feature of this invention is the direction of a pen input on an electronic device to a separate canvas where it can be separately manipulated and...
US-9,141,132 Multi-protocol I/O interconnect time synchronization
Described are embodiments of methods, apparatuses, and systems for time synchronization of a multi-protocol I/O interconnect of computer apparatus. A method for...
US-D739,400 Electronic computer with an at least partially transparent input device
US-D739,399 Electronic computer with an at least partially transparent input device
US-D739,398 Electronic computer with an at least partially transparent input device
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