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Patent # Description
US-9,912,774 Accelerated network packet processing
Devices and techniques for accelerated packet processing are described herein. The device can match an action to a portion of a network data packet and...
US-9,912,704 System, apparatus and method for access control list processing in a constrained environment
In one embodiment, a method includes receiving a first request from a first device to access a first resource of the system and determining whether to grant...
US-9,912,645 Methods and apparatus to securely share data
Methods and apparatus to securely share data are disclosed. An example includes retrieving, by executing an instruction with a processor at a first computing...
US-9,912,602 Multi-radio communication between wireless devices
In various embodiments, two wireless communication devices may communicate with each other using multiple protocols, by dividing the data to be communicated...
US-9,912,558 Techniques for monitoring virtualized network functions or network functions virtualization infrastructure
Examples may include techniques for monitoring virtual network functions or network functions virtualization infrastructure. Examples include receiving...
US-9,912,489 Multiple-user request-to-send frames in a high-efficiency wireless local-area network (HEW)
Apparatuses, computer readable media, and methods for sending and receiving multi-user request-to-send frames in a high-efficiency wireless local-area network...
US-9,912,481 Method and apparatus for efficiently executing hash operations
An apparatus and method are described for executing hash functions on a processor. For example, one embodiment of a processor comprises: a register set...
US-9,912,474 Performing telemetry, data gathering, and failure isolation using non-volatile memory
Methods and apparatus related to performance of telemetry, data gathering, and failure isolation using non-volatile memory are described. In one embodiment, a...
US-9,912,462 Apparatus, computer readable medium, and method for alignment of long training fields in a high efficiency...
Apparatuses, computer readable media, and methods for extending a long-training field are disclosed. An apparatus of a high-efficiency (HE) wireless local-area...
US-9,912,452 High efficiency signal field encoding structure
This disclosure describes methods, apparatus, and systems related to a high efficiency signal field encoding structure. A device may determine a communications...
US-9,912,449 Internet protocol interface selection for routing data traffic
A technology for a user equipment (UE) that is operable to select an internet protocol (IP) interface in a communications network is disclosed. Local policy...
US-9,912,442 Techniques to perform forward error correction for an electrical backplane
Data is received from a physical coding sublayer (PCS) of a physical layer, where the physical layer comprises a BASE-R physical layer. The data is used to...
US-9,912,425 Radio frequency transceiver with local oscillator control for multi-carrier applications
Radio frequency (RF) communication circuitry comprises an RF transceiver and conflict detection circuitry. The RF transceiver includes a first communication...
US-9,912,357 Digital polar transmitter having a digital front end
A digital polar transmitter arrangement having a digital front end (DFE) and a transmit chain is disclosed. The DFE is configured to resample a baseband signal...
US-9,912,355 Distributed concatenated error correction
In one embodiment, a distributed concatenated error correction logic is disposed on separate integrated circuit dies to facilitate efficiency. In one...
US-9,912,176 Template battery and circuit design thereof
A template battery comprises one or more layers that fill into a dead space on a substrate. The substrate comprises one or more components. The one or more...
US-9,912,164 Multisource power delivery system
One embodiment provides an apparatus. The apparatus includes a plurality of storage elements coupled in series. The storage elements are to capture and store...
US-9,911,835 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and...
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling...
US-9,911,815 Extended-drain structures for high voltage field effect transistors
Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate...
US-9,911,807 Strain compensation in transistors
Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The...
US-9,911,723 Magnetic small footprint inductor array module for on-package voltage regulator
An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements...
US-9,911,694 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed...
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to...
US-9,911,689 Through-body-via isolated coaxial capacitor and techniques for forming same
Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor...
US-9,911,509 Counter to locate faulty die in a distributed codeword storage system
Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment,...
US-9,911,386 Efficient luminous display
In one embodiment a display assembly comprises a liquid crystal module, a backlight assembly comprising an array of light emitting diodes, a timing controller,...
US-9,911,219 Detection, tracking, and pose estimation of an articulated body
Techniques related to pose estimation for an articulated body are discussed. Such techniques may include extracting, segmenting, classifying, and labeling...
US-9,911,107 Automated secure check-out and drop-off return of products using mobile device
Generally, this disclosure describes a method and system for automated check-out and drop-off return of products using a mobile device. A method may include...
US-9,910,972 Remote trust attestation and geo-location of servers and clients in cloud computing environments
Methods and systems may provide for selecting a hypervisor protocol from a plurality of hypervisor protocols based on a communication associated with a remote...
US-9,910,814 Method, apparatus and system for single-ended communication of transaction layer packets
Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated...
US-9,910,809 High performance interconnect link state transitions
A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent...
US-9,910,807 Ring protocol for low latency interconnect switch
Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed...
US-9,910,796 Programmable event driven yield mechanism which may activate other threads
Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes...
US-9,910,793 Memory encryption engine integration
Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a...
US-9,910,792 Composite field scaled affine transforms-based hardware accelerator
A processing system includes a memory and a cryptographic accelerator operatively coupled to the memory. The cryptographic accelerator performs a split...
US-9,910,790 Using a memory address to form a tweak key to use to encrypt and decrypt data
Provided are a memory system, memory controller, and method for using a memory address to form a tweak key to use to encrypt and decrypt data. A base tweak co...
US-9,910,786 Efficient redundant array of independent disks (RAID) write hole solutions
Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power...
US-9,910,771 Non-volatile memory interface
In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a...
US-9,910,728 Method and apparatus for partial cache line sparing
Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having...
US-9,910,721 System and method for execution of application code compiled according to two instruction set architectures
Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime...
US-9,910,699 Virtual processor direct interrupt delivery mechanism
A method comprising is described. The method includes receiving an interrupt targeting a virtual processor, determining a status of the virtual processor and...
US-9,910,692 Enhanced virtual function capabilities in a virtualized network environment
The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and...
US-9,910,670 Instruction set for eliminating misaligned memory accesses during processing of an array having misaligned data...
A processor is described having an instruction execution pipeline. The instruction execution pipeline includes an instruction fetch stage to fetch an...
US-9,910,669 Instruction and logic for characterization of data access
A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit...
US-9,910,650 Method and apparatus for approximating detection of overlaps between memory ranges
A computer-implemented method for managing loop code in a compiler includes using a conflict detection procedure that detects across-iteration dependency for...
US-9,910,646 Technologies for native code invocation using binary analysis
Technologies for native code invocation using binary analysis are described. A computing device for invoking native code from managed code using binary analysis...
US-9,910,611 Access control for memory protection key architecture
A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a...
US-9,910,604 Refresh parameter-dependent memory refresh management
Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory...
US-9,910,498 System and method for close-range movement tracking
A system and method for close range object tracking are described. Close range depth images of a user's hands and fingers or other objects are acquired using a...
US-9,910,484 Voltage regulator training
Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system....
US-9,910,483 Distribution of tasks among asymmetric processing elements
Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate...
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