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Patent # Description
US-1,026,4492 Apparatus, method and system of establishing a transmission opportunity (TxOP)
Some demonstrative embodiments include apparatuses, devices, systems and methods of communicating a wide-bandwidth data frame. For example, an apparatus may...
US-1,026,4482 Enhanced node B configured for user plane EPS optimization
When a UE in an LTE system enters the RRC_IDLE state, only the S5/S8 EPS bearer context is retained, and the S1-U, S1-AP and radio bearers are released. These...
US-1,026,4397 Apparatus, computer-readable medium, and method to determine a user equipment location in a cellular network...
An apparatus, computer-readable medium, and method to determine a user equipment (UE) location in a wireless network using signals from a wireless local-area...
US-1,026,4313 Dynamic media content output for mobile devices
Embodiments of mechanisms for dynamic media content type streaming management for mobile devices are generally described herein. In some embodiments, the mobile...
US-1,026,4169 System to synchronize flashes between mobile devices
Systems, apparatuses and methods for conducting collaborative sessions between mobile devices may provide for identifying the external mobile devices within a...
US-1,026,3988 Protected container key management processors, methods, systems, and instructions
A processor of an aspect includes a decode unit to decode an instruction. The instruction to indicate a first structure in a protected container memory and to...
US-1,026,3769 Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes...
US-1,026,3750 Cross indication of queue size in a reverse direction protocol
This disclosure describes systems, methods, and computer-readable media related to cross indication of queue size in a reverse direction protocol. In some...
US-1,026,3707 Electro-optical modulator with differential bias control
Embodiments of the present disclosure are directed toward techniques and configurations for an apparatus comprising an electro-optical modulation device with a...
US-1,026,3663 M-ary pulse amplitude modulation digital equalizer
Some embodiments include apparatus and methods using an input node, an analog to digital converter (ADC) including an input coupled to the input node, a first...
US-1,026,3637 Technologies for performing speculative decompression
Technologies for performing speculative decompression include a managed node to decode a variable size code at a present position in compressed data with a...
US-1,026,3624 Phase synchronization between two phase locked loops
Systems, methods, and circuitries for synchronizing a first phase locked loop (PLL) with a second PLL are provided. In one example a PLL system includes a first...
US-1,026,3451 Coil for mobile device context-driven switching and wireless charging
Apparatus, system and method to provide switchable coils in a computing device, comprising: a plurality of electrically conductive coils to transfer...
US-1,026,3450 Power regulation in wireless charging
Techniques for power regulation in a system, method, and apparatus are described herein. An apparatus for voltage regulation in a wireless power receiver may...
US-1,026,3346 Single-package phased array module with interleaved sub-arrays
Embodiments of the present disclosure are directed to a single-package communications device that includes an antenna module with a plurality of independently...
US-1,026,3312 Plurality of dielectric waveguides including dielectric waveguide cores for connecting first and second server...
A method of making a waveguide ribbon that includes a plurality of waveguides comprises joining a first sheet of dielectric material to a first conductive sheet...
US-1,026,3112 Vertical non-planar semiconductor device for system-on-chip (SoC) applications
Vertical non-planar semiconductor devices for system-on-chip (SoC) applications and methods of fabricating vertical non-planar semiconductor devices are...
US-1,026,3106 Power mesh-on-die trace bumping
A power mesh-on-die apparatus includes a solder trace that enhances current flow for a power source trace between adjacent power bumps. The solder trace is also...
US-1,026,3079 Apparatus and methods for forming a modulation doped non-planar transistor
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors...
US-1,026,3074 High voltage field effect transistors
Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A...
US-1,026,3036 Strain assisted spin torque switching spin transfer torque memory
Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) having a free magnetic layer; a piezoelectric layer; and a conducting strain...
US-1,026,2754 Fine grained online remapping to handle memory errors
An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is...
US-1,026,2751 Multi-dimensional optimization of electrical parameters for memory training
Aspects of the embodiments are directed to systems, methods, and devices for generating a design of experiments (DOE) matrix, the DOE matrix comprising a set of...
US-1,026,2716 Temperature dependent modes of operation of a semiconductor memory device
A first threshold temperature is maintained for operating a solid state drive (SSD) in a first mode. A second threshold temperature is maintained for operating...
US-1,026,2599 Display backlight brightness adjustment
In some examples, a display includes a plurality of display backlight groups, and one or more controller to determine one or more one-dimensional backlight...
US-1,026,2464 Dynamic, local augmented reality landmarks
In some embodiments, the disclosed subject matter involves a system and method relating to dynamically sending local visual landmark information from multiple...
US-1,026,2456 Method and apparatus for extracting and using path shading coherence in a ray tracing architecture
An apparatus and method for extracting and using path shading coherence in a ray tracing architecture. For example, one embodiment of a graphics processing...
US-1,026,2455 Merging fragments for coarse pixel shading using a weighted average of the attributes of triangles
Two primitives may be merged by interpolating vertex attributes at coarse pixel centers. Input attributes are computed as a coverage weighted average of the...
US-1,026,2397 Image de-noising using an equalized gradient space
Image de-noising is described using an equalized gradient space. In one example, a method of de-noising an image includes determining an intensity gradient...
US-1,026,2394 Tracking objects in bowl-shaped imaging systems
Technologies for determining a distance of an object from a vehicle include a computing device to identify an object captured in a fisheye image generated by a...
US-1,026,2393 Multi-sample anti-aliasing (MSAA) memory bandwidth reduction for sparse sample per pixel utilization
Methods and apparatus relating to Multi-Sample Anti-Aliasing (MSAA) memory bandwidth reduction for sparse sample per pixel utilization are described. In an...
US-1,026,2388 Frequent data value compression for graphics processing units
A control surface tracks an individual cacheline in the original surface for frequent data values. If so, control surface bits are set. When reading a cacheline...
US-1,026,2237 Technologies for improved object detection accuracy with multi-scale representation and training
Technologies for multi-scale object detection include a computing device including a multi-layer convolution network and a multi-scale region proposal network...
US-1,026,2162 Control transfer termination instructions of an instruction set architecture (ISA)
In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic...
US-1,026,2140 Methods and apparatus to facilitate blockchain-based boot tracking
A device with support for blockchain-based boot tracking comprises at least one processor, non-volatile storage responsive to the processor, and at least one...
US-1,026,2077 Systems and methods for pattern matching and relationship discovery
Methods and systems for pattern matching and relationship discovery in graphs. The graph may be adapted as an actor graph, where vertices may include processing...
US-1,026,1923 Configurable interconnect apparatus and method
Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least...
US-1,026,1909 Speculative cache modification
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing a speculative...
US-1,026,1904 Memory sequencing with coherent and non-coherent sub-systems
Operations associated with a memory and operations associated with one or more functional units may be received. A dependency between the operations associated...
US-1,026,1903 Extend GPU/CPU coherency to multi-GPU cores
In an example, an apparatus comprises a plurality of processing unit cores, a plurality of cache memory modules associated with the plurality of processing unit...
US-1,026,1901 Method and apparatus for unneeded block prediction in a computing system having a last level cache and a...
An apparatus is described. The apparatus includes a last level cache and a memory controller to interface to a multi-level system memory. The multi-level system...
US-1,026,1879 Instruction and logic to test transactional execution status
Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start...
US-1,026,1859 Bypassing error correction code (ECC) processing based on software hint
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially...
US-1,026,1858 TCAM soft-error detection method and apparatus
Apparatuses, methods and storage medium associated with techniques to detect soft errors of a TCAM are disclosed herein. In embodiments, an apparatus may...
US-1,026,1854 Memory integrity violation analysis method and apparatus
Methods, apparatus, and system to analyze a memory integrity violation and determine whether its cause was hardware or software based.
US-1,026,1814 Local service chaining with virtual machines and virtualized containers in software defined networking
Methods, software, and apparatus for implementing local service chaining (LSC) with virtual machines (VMs) or virtualized containers in Software Defined...
US-1,026,1795 Instruction and logic for processing text strings
Method, apparatus, and program means for performing a string comparison operation. In one embodiment, an apparatus includes execution resources to execute a...
US-1,026,1792 Method and apparatus for obtaining a call stack to an event of interest and analyzing the same
In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where...
US-1,026,1790 Memory copy instructions, processors, methods, and systems
A processor includes a decode unit to decode a memory copy instruction that indicates a start of a source memory operand, a start of a destination memory...
US-1,026,1788 Processors, methods, systems, and instructions to transcode variable length code points of unicode characters
A processor includes a plurality of packed data registers. The processor also includes a decode unit to decode a packed variable length code point length...
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