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| Patent # | Description |
|---|---|
| US-9,444,655 |
Apparatus, method and system of scrambling a wireless transmission Some demonstrative embodiments include devices, systems and methods of scrambling wireless transmissions. For example, an apparatus may include a selector to... |
| US-9,444,627 |
System and method for providing global platform compliant trusted
execution environment Method of providing a Global Platform (GP) compliant Trusted Execution Environment (TEE) starts with main processor executing an application stored in memory... |
| US-9,444,569 |
Method to identify and differentiate background traffic Embodiments of a system and method to identify and differentiate background traffic are generally described herein. In some embodiments, a transceiver is... |
| US-9,444,551 |
High performance optical repeater An optical element is to be coupled to a second device by the second electrical link. The particular optical element is further to receive a first signal from... |
| US-9,444,522 |
Near field communications (NFC) coil and proximity sensor for portable
devices Described herein are techniques related to near field coupling and proximity sensing operations. For example, a proximity sensor uses a coil antenna that is... |
| US-9,444,511 |
Plug-and-play time-variant antenna module for wireless communication
devices A plug-and-play antenna may be used with many different types of wireless communication devices. An antenna may be coupled to an impedance tuning component and... |
| US-9,444,509 |
Non-blocking power management for on-package input/output architectures An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no... |
| US-9,444,492 |
High performance interconnect link layer Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more... |
| US-9,444,486 |
Digital to analog converter comprising mixer One example described herein relates to a digital to analog converter (DAC). The DAC includes a digital signal input configured to receive a multi-bit digital... |
| US-9,444,328 |
Acoustic noise mitigation using periodicity disruption In one or more embodiments, a fixed time interval for a system is determined. The fixed time interval corresponds to time between clock ticks. A random time... |
| US-9,444,140 |
Multi-element antenna beam forming configurations for millimeter wave
systems Multiple transmit antenna beam formers include/share a same set of power amplifiers and antenna elements to form multiple concurrent transmit antenna beams.... |
| US-9,443,980 |
Pulsed laser anneal process for transistors with partial melt of a raised
source-drain A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack... |
| US-9,443,936 |
Quantum well MOSFET channels having lattice mismatch with metal
source/drains, and conformal regrowth source/drains Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a... |
| US-9,443,922 |
Metal-insulator-metal capacitor formation techniques Techniques and structure are disclosed for providing a MIM capacitor having a generally corrugated profile. The corrugated topography is provisioned using... |
| US-9,443,864 |
Self-aligned floating gate in a vertical memory structure A memory device or electronic system may include a memory cell body extending from a substrate, a self-aligned floating gate separated from the memory cell body... |
| US-9,443,600 |
Auto-suspend and auto-resume operations for a multi-die NAND memory device
to reduce peak power consumption A method and apparatus that controls a peak-current condition in a multi-die memory, such as a solid-state drive, by determining by at least one die of the... |
| US-9,443,567 |
High speed sense amplifier latch with low power rail-to-rail input common
mode range Described is an apparatus which comprises: an input sensing stage for sensing an input signal relative to another signal; a decision making circuit, coupled to... |
| US-9,443,347 |
Time-continuous collision detection using 3D rasterization We present a technique that utilizes a motion blur (three dimensional) rasterizer to augment the PCS culling technique so that it can be used for continuous... |
| US-9,443,307 |
Processing of images of a subject individual A computing system receives a plurality of candidate images of a subject individual and generates pose data for each of the candidate images. The pose data of a... |
| US-9,443,281 |
Pixel-based warping and scaling accelerator Technologies are presented that allow efficient pixel-based image and/or video warping and scaling. An image processing system may include a memory and an... |
| US-9,443,280 |
Selective hardware acceleration in video playback systems Embodiments of a system and method for enhanced video performance in a video playback system are generally described herein. In some embodiments, a video frame... |
| US-9,443,279 |
Direct link synchronization communication between co-processors Systems, apparatus, articles, and methods are described including operations to communicate synchronization notifications between a co-processor graphic data... |
| US-9,443,272 |
Methods and apparatus for providing improved access to applications A data processing system includes components for providing a pleasant user experience. Those components may include a family interaction engine that provides a... |
| US-9,443,096 |
Systems and methods for controlling access to supplemental content
integrated into existing content Methods and systems to allow for selective access to supplemental content that is associated with more generally distributed original content. In an embodiment,... |
| US-9,442,879 |
Multiple transaction data flow control unit for high-speed interconnect Methods, apparatus, and systems, for transporting data units comprising multiple pieces of transaction data over high-speed interconnects. A flow control unit,... |
| US-9,442,871 |
Accessing data stored in a command/address register device A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by... |
| US-9,442,868 |
Delivering interrupts directly to a virtual processor Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an... |
| US-9,442,865 |
Processor extensions for execution of secure embedded containers Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for... |
| US-9,442,864 |
Bridging circuitry between a memory controller and request agents in a
system having multiple system memory... A processor is described that includes one or more processing cores. The processor includes a memory controller to interface with a system memory having a... |
| US-9,442,861 |
System and method for out-of-order prefetch instructions in an in-order
pipeline Apparatuses, systems, and a method for providing a processor architecture with data prefetching are described. In one embodiment, a system includes one or more... |
| US-9,442,855 |
Transaction layer packet formatting A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is... |
| US-9,442,849 |
Apparatus and method for reduced core entry into a power state having a
powered down core cache A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the... |
| US-9,442,826 |
Kernel functionality checker A debugging system and method, referred to as a kernel functionality checker, is described for enabling debugging of software written for device-specific APIs... |
| US-9,442,739 |
Collaborative processor and system performance and power management The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more... |
| US-9,442,733 |
Packed data operation mask comparison processors, methods, systems, and
instructions Receive packed data operation mask comparison instruction indicating first packed data operation mask having first packed data operation mask bits and second... |
| US-9,442,731 |
Packed two source inter-element shift merge processors, methods, systems,
and instructions A processor includes a decoder to receive an instruction that indicates first and second source packed data operands and at least one shift count. An execution... |
| US-9,442,729 |
Minimizing bandwidth to track return targets by an instruction tracing
system A processing device implementing minimizing bandwidth to track return targets by an instruction tracing system is disclosed. A processing device of the... |
| US-9,442,723 |
Method and apparatus for integral image computation instructions A method is described that performing an image integral calculation by creating a second vector and creating a third vector. The second vector is created by... |
| US-9,442,721 |
Method and system to provide user-level multithreading A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming... |
| US-9,442,559 |
Exploiting process variation in a multicore processor A disclosed method includes accessing characterization data indicating first and second sets of performance characteristics for first and second processing... |
| US-9,442,558 |
Techniques and system for managing activity in multicomponent platform In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor... |
| US-9,442,463 |
Time-to-digital converter (TDC) with offset cancellation Described is an apparatus which comprises: a switching device to receive first and second inputs, and to generate first and second outputs; and a ... |
| US-9,442,286 |
Spaced configuration of acousto-optic deflectors for laser beam scanning
of a semiconductor substrate A first acousto-optic deflector receives a laser beam. The first acousto-optic deflector diffracts the received laser beam along a first axis. A second... |
| US-9,441,952 |
Metrology tool for electroless copper thickness measurement for BBUL
process development monitoring A method including measuring a first distance to a surface of an integrated circuit substrate or a portion of an integrated circuit package by measuring an... |
| US-D766,234 |
Wearable electronic display device with an attachable accent |
| US-D766,233 |
Electronic device |
| US-9,439,208 |
Scheduling requests for wireless communication devices running background
applications In embodiments, a user equipment (UE) may transmit, to an evolved Node B (eNB), a background indicator that the UE is in a background mode running one or more... |
| US-9,439,206 |
Method for controlling measurements in a wireless telecommunications
terminal A method is provided for controlling measurements in a wireless telecommunications terminal. In a Long Term Evolution (LTE) wireless communication system, the... |
| US-9,439,148 |
Methods and arrangements for channel access in wireless networks Embodiments may define traffic priorities to facilitate transmissions for wireless communications devices. Many embodiments comprise MAC sublayer logic to... |
| US-9,439,147 |
Mechanisms of reducing power consumption for NAN devices A wireless communication device comprises a transceiver configured to communicate information with one or more neighbor devices in accordance with a sync mode... |
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