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Methods and apparatus for modeling and simulating spintronic integrated
Described are apparatus and method for simulating spintronic integrated circuit (SPINIC), the method comprising: generating a spin netlist indicating...
Partitioned bluetooth system
A system includes a first memory, a second memory, a host processor, and a second processor. The first memory is configured to store first layers of a Bluetooth...
Dead block predictors for cooperative execution in the last level cache
A cache memory eviction method includes maintaining thread-aware cache access data per cache block in a cache memory, wherein the cache access data is...
Mechanisms to accelerate transactions using buffered stores
In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in...
Adaptive configuration of non-volatile memory
Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values...
Dynamic operations for 3D stacked memory using thermal data
Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory...
Enhanced storage of metadata utilizing improved error detection and
correction in computer memory
A novel ECC scheme is disclosed that offers an error protection level that is at least the same as (if not better than) that of the conventional ECC scheme...
Cache coherency and processor consistency
Responsive to execution of a computer instruction in a current translation window, state indicators associated with a cache line accessed for the execution may...
Tracking written addresses of a shared memory of a multi-core processor
Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the...
Exposing protected memory addresses
Mechanisms for exposing a protected memory address are provided. A processing device may store a data value at a protected memory address. The protected memory...
Keyboard with magnetic key position return for an electronic device
Particular embodiments described herein provide for a keyboard assembly having a plurality of keys that include a key having one or more magnets, which are...
Controlling reduced power states using platform latency tolerance
In an embodiment, a processor includes a plurality of cores and power management logic. The power management logic may be to, in response to a first break event...
Techniques for platform duty cycling
Various embodiments are generally directed to an apparatus, method and other techniques for detecting active and semi-active workloads during execution on a...
Inverted 45 degree mirror for photonic integrated circuits
Inverted 45.degree. semiconductor mirrors as vertical optical couplers for PIC chips, particularly optical receivers and transmitters. An inverted 45.degree....
Hardware-efficient on-chip calibration of analog/RF through sub-sampling
A digital on-die-test engine (OTE) generates stimuli signals for an analog/RF circuit, where the OTE is embedded within the circuitry. The stimuli signals are...
Identification-assisted wireless network connections
Systems and methods for transmitting location-specific information such as wireless network connectivity information are generally disclosed herein. One...
Communication device and method for communicating in a communication mode
using a frequency range according to...
According to one embodiment, a communication device is described comprising a communication circuit configured to communicate in a first communication mode...
Directional transmission techniques
Embodiments provide techniques for the transmission of broadcasts. For instance, an apparatus may include a sequence selection module, and multiple radiating...
High efficiency distributed device-to-device (D2D) channel access
Techniques for facilitating device-to-device (D2D) communications using a high efficiency distributed channel access scheme are generally described herein. In...
System, methods, and computer program products for multi-stream
Methods, systems and computer program products for the synchronization of media streams. In an embodiment, a gross synchronization may first be performed on the...
Physical uplink control channel (PUCCH) resource allocation (RA) for a
hybrid automatic retransmission...
Technology to provide physical uplink control channel (PUCCH) resource allocation in time division duplex (TDD) for a hybrid automatic retransmission...
Digital wideband closed loop phase modulator with modulation gain
One embodiment of the present invention relates to a modulation system having a phase locked loop and an adaptive control. The phased lock loop is configured to...
Digital NRZI signal for serial interconnect communications between the
link layer and physical layer
Systems and methods of operating a serial interconnect interface provide for generating a pulse in response to a state change in a data signal of the serial...
Enhanced node B and method for RRC connection establishment for small data
Embodiments of an enhanced Node B (eNB) and method for RRC connection establishment for small-data transfers in a 3GPP LTE network are generally described...
Communication device and method for packet-based OFDM communications with
differing length cyclic prefixes
A network communication device is receive packet-based orthogonal frequency division multiplexed (OFDM) transmissions from one or more other devices in a...
Method for control channel detection in wireless communications systems
A method of detecting a control channel includes receiving data transmitted via a control channel. A path metric and a correction term is computed based on the...
Techniques for low power visual light communication
Various embodiments are generally directed to techniques for reducing the consumption of electric power in decoding VLC frame patterns by selectively decoding...
Techniques for transmitting data via relay communication links
Examples are disclosed for transmitting data via a relay communication links. In some examples, a wireless device may receive a packet having a physical layer...
Apparatus, system, and method for re-synthesizing a clock signal
Described herein are apparatus, method, and system for re-synthesizing a clock signal. The apparatus comprises: a first logic unit to detect a rising edge of an...
A first stage of a digital filter receives input data to be filtered, the first stage of a digital filter operating at a first clock; a second stage of the...
Circuit, transceiver and mobile communication device
A circuit for providing a bias signal for a power amplifier includes a first input, a second input and an output. The first input is configured to receive an...
Digital event generator, comparator, switched mode energy converter and
A digital event generator includes a counter configured to provide at least one count value based on a clock signal, and a comparator configured to evaluate a...
Reduced size cavity filter for PICO base stations
An improved microwave cavity filter used in cellular communication systems such as base stations is disclosed. The cavity filter has a conductive housing...
Nonplanar device with thinned lower body portion and method of fabrication
A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a...
Local buried channel dielectric for vertical NAND performance enhancement
and vertical scaling
A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. The memory device utilizes a local buried channel dielectric...
Using an optically transparent solid material as a support structure for
attachment of a semiconductor material...
Electronic devices and methods for fabricating electronic devices are described. One method includes attaching an optically transparent solid material to a body...
High density substrate routing in BBUL package
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more...
Enabling package-on-package (PoP) pad surface finishes on bumpless
build-up layer (BBUL) package
A bumpless build-up layer (BBUL) integrated circuit package and method of manufacturing are presented. In some embodiments, the package-on-package (PoP) pads of...
Generic data scrambler for memory circuit test engine
A generic data scrambler is provided for a built-in self-test (BIST) engine of a stacked memory device. The stacked memory device includes a memory stack of one...
Multi-level memory with direct access
Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes...
Visual indicator and adjustment of media and gaming attributes based on
Systems and methods may provide for identifying an amount of time associated with a user based activity with respect to a battery powered device, and...
Method and device for processing digital image, and computer-readable
recording medium for processing digital image
There is provided a method of processing a digital image including: (a) obtaining a plurality of images; (b) converting the plurality of images into histograms;...
Protecting a software component using a transition point wrapper
Embodiments of apparatuses, articles, methods, and systems for protecting software components using transition point wrappers are generally described herein. In...
Apparatus and method for implementing zero-knowledge proof security
techniques on a computing platform
An apparatus and method for zero knowledge proof security techniques within a computing platform. One embodiment includes a security module executed on a...
Method and device for synchronizing data broadcasts for system-on-chip
A method and a device for synchronizing broadcast of streaming data by a transmitting data processing unit to a plurality of receiving data processing units is...
Dual casting PCIE inbound writes to memory and peer devices
Methods and apparatus for supporting dual casting of inbound system memory writes from PCIe devices to memory and a peer PCIe device. An inbound system memory...
Interface logic for a multi-core system-on-a-chip (SoC)
In one embodiment, the present invention includes a system-on-a-chip (SoC) with first and second cores, interface logic coupled to the cores, chipset logic...
Protected access to virtual memory
Embodiments of techniques and systems for protected access to virtual memory are described. In embodiments, a protected memory management architecture ("PMMA")...
Logging in secure enclaves
Embodiments of an invention for logging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The...
Apparatus and method for memory-mapped register caching
A processor is described comprising: an architectural register file implemented as a combination of a register file cache and an architectural register region...