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Patent # Description
US-9,231,753 Low power oversampling with reduced-architecture delay locked loop
In one embodiment, an apparatus including a phase detector unit to determine a phase difference between an inverted reference clock signal and a feedback clock...
US-9,231,740 Transmitter noise in system budget
One embodiment provides an apparatus. The example apparatus includes a root mean square (RMS) distortion determination module configured to determine an RMS...
US-9,231,723 Coordinated dynamic point selection (DPS) with cell range expansion in a coordinated multipoint (CoMP) system
Technology for mitigating edge effect interference in a Coordinated MultiPoint (CoMP) system having multiple CoMP clusters is disclosed. In an example, a method...
US-9,231,714 Methods for calibrating a transmitter, and radio transmitter
In an embodiment, a radio transmitter may be provided. The radio transmitter may include a radio transmitter control loop; and a controller configured in such a...
US-9,231,681 Apparatus, system and method of wireless backhaul and access communication via a common antenna array
Some demonstrative embodiments include apparatuses, systems and/or methods of wireless backhaul and access communication via a common antenna array. For...
US-9,231,675 Receiver and method for detecting a pre-coded signal
A multi-user MIMO receiver of a UE in question for detecting a pre-coded signal includes a unit configured to blindly estimate information concerning a...
US-9,231,602 A-priori-probability-phase-estimation for digital phase-locked loops
A digital phase locked loop operates with a time-to-digital converter and an a-priori-probability-phase-estimation component or estimator component that...
US-9,231,561 Multi-stage adaptive filter
A multi-stage adaptive filter is disclosed, which exhibits a smaller mean square error than in prior art adaptive filters. The adaptive filter selectively...
US-9,231,524 Digital transceiver with switched capacitor sampling mixers and switched capacitor amplifiers
Examples of a digital transceiver, a switched-capacitor sampling mixer, and an N-stage switched-capacitor amplifier are generally described herein. The digital...
US-9,231,519 Temperature compensation for oscillator
A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature...
US-9,231,434 Charging a battery using a multi-rate charge
A method and system for applying a multi-rate charge to a battery are included herein. The method includes detecting a plurality of predetermined electrical...
US-9,231,331 Connector identification through proximity sensing
A computing device is disclosed herein. The computing device includes a connector port and a near field communication (NFC) transceiver/receiver to identify a...
US-9,231,318 Integrated package insertion and loading mechanism (iPILM)
A holding member and system including a first holding member and a second holding member, wherein each of the first holding member and the second holding member...
US-9,231,204 Low voltage embedded memory having conductive oxide and electrode stacks
Embodiments include low voltage embedded memory having conductive oxide and electrode stacks. A material layer stack for a memory element includes a first...
US-9,231,202 Thermal-disturb mitigation in dual-deck cross-point memories
A thermal isolation layer is formed between the bit line (BL) layers or word line (WL) layers of the decks of a multi-deck phase-change cross-point memory to...
US-9,231,194 High stability spintronic memory
An embodiment includes a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed...
US-9,231,076 Enhanced dislocation stress transistor
A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at...
US-9,230,944 Techniques and configurations associated with a capductor assembly
Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor...
US-9,230,900 Ground via clustering for crosstalk mitigation
Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated...
US-9,230,877 Methods of forming serpentine thermal interface material and structures formed thereby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal...
US-9,230,833 Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection...
Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures...
US-9,230,636 Apparatus for dual purpose charge pump
Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node;...
US-9,230,614 Separate microchannel voltage domains in stacked memory architecture
Separate microchannel voltage domains in a stacked memory architecture An embodiment of a memory device includes a memory stack including one or more coupled...
US-9,230,297 Systems, methods, and computer program products for compound image demosaicing and warping
Methods, systems, and computer program products to obtain a color image from a color filter array, such as, for example, a color filter array comprising a Bayer...
US-9,230,139 Selective content sharing on computing devices
Described herein are architectures, platforms and methods for selective content sharing feature between computing devices, and particularly, a system that...
US-9,230,120 Architecture and instruction set for implementing advanced encryption standard (AES)
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard...
US-9,230,116 Technique for providing secure firmware
A technique to verify firmware. One embodiment of the invention uses a processor's micro-code to verify a system's firmware, such that the firmware can be...
US-9,230,081 User authorization and presence detection in isolation from interference from and control by host central...
An embodiment may include circuitry to be included, at least in part, in a host. The host may include at least one host central processing unit (CPU) to...
US-9,230,032 Poll-based networking system
Described is a poll-based networking system. The system provides an on-line network of friends that are determined through polling each of the users. This...
US-9,229,897 Embedded control channel for high speed serial interconnect
Methods and apparatus for embedding a control channel in a high speed serial interconnect having multiple data lanes. Operational aspects of the interconnect...
US-9,229,895 Multi-core integrated circuit configurable to provide multiple logical domains
Apparatuses, methods and storage media associated with integrated circuits (IC) or system-on-chips (SOC) are disclosed herein. In embodiments, a multi-core IC...
US-9,229,879 Power reduction using unmodified information in evicted cache lines
Embodiments of the present disclosure describe techniques and configurations to reduce power consumption using unmodified information in evicted cache lines. A...
US-9,229,874 Apparatus and method for compressing a memory address
An apparatus and method for converting between a full memory address and a compressed memory address. For example, one embodiment comprises one or more...
US-9,229,872 Semiconductor chip with adaptive BIST cache testing during runtime
A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die...
US-9,229,853 Method and system for data de-duplication
An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may...
US-9,229,836 Coexisting standard and proprietary connection usage
A method for coexisting standard connection and proprietary connection use is disclosed. The method may include connecting a peripheral device to a host...
US-9,229,828 Mechanism for achieving high memory reliability, availability and serviceability
A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of...
US-9,229,761 Generating, at least in part, at least one packet indicating, at least in part, at least one command and/or...
An embodiment may include circuitry to be included, at least in part, in a node in a network. The circuitry may expose, at least in part, a virtual function...
US-9,229,720 Circuit marginality validation test for an integrated circuit
A high volume manufacturing (HVM) and circuit marginality validation (CMV) test for an integrated circuit (IC) is disclosed. The IC comprises a port binding and...
US-9,229,719 Method and apparatus for shuffling data
Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a...
US-9,229,718 Method and apparatus for shuffling data
Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a...
US-9,229,524 Performing local power gating in a processor
In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution...
US-9,229,517 Computer input device power savings
In some embodiments a computing device includes a holder to hold an input device, a detector to detect whether the input device is held by the holder, and a...
US-9,229,466 Fully integrated voltage regulators for multi-stack integrated circuit architectures
A voltage regulator for one or more dies in a multi-stack integrated circuit includes an inductor located on a die, a voltage controller that is electrically...
US-9,229,054 Self-contained, path-level aging monitor apparatus and method
An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a...
US-D746,821 Electronic device with retractable leg support
US-9,219,801 Implementing a protocol adaptation layer over an internet protocol
A system and method are provided that allow WiGig protocol adaptation layers (PALs) to operate differently from the proposed WiGig standard on top of an...
US-9,219,725 Method, apparatus, and system for sending credentials securely
A software application executing in a first local operating environment may be used to connect to a remote server that requires a credential of a user to...
US-9,219,623 Adaptive delay base loss equalization
A method, system and apparatus to self-determine equalization parameters for a channel. An initiator sends an equalization insensitive signal (EIS) to a...
US-9,219,602 Method and system for securely computing a base point in direct anonymous attestation
A method and system computes a basepoint for use in a signing operation of a direct anonymous attestation scheme. The method and system includes computing a...
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