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Patent # Description
US-1,001,5048 Programmable protocol parser for NIC classification and queue assignments
Technologies for controlling operation of a compute node coupled to a computer network via a computing device that includes communications for communicating...
US-1,001,5037 Generation of a transmission signal
One embodiment covers an apparatus for generating a transmission signal. The apparatus may include a signal generator that generates a first signal with a first...
US-1,001,5036 Systems and methods for modulation and coding scheme selection and configuration
Methods, systems, and devices for modulation and coding scheme selection and configuration. A mobile communication device includes a table component, a table...
US-1,001,5014 Technologies for secure presence assurance
Technologies for secure presence assurance include a computing device having a presence assertion circuitry that receives an input seed value and generates a...
US-1,001,5010 SM4 acceleration processors, methods, systems, and instructions
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode an instruction. The instruction is to indicate one or more...
US-1,001,4994 Wireless devices, computer-readable media, and methods for high-efficiency local-area network (HEW) distributed...
Methods, devices and a computer-readable medium are disclosed for subcarrier allocation to multiple users in wireless local-area networks in accordance with...
US-1,001,4960 Methods and systems for determining a human body channel sensor position
A technology is described for determining a position of a HBC (Human Body Channel) sensor. An example method may include receiving signal data for a radio...
US-1,001,4924 Antenna array weight vector selection techniques for 60 GHz MIMO communications
Various embodiments may be generally directed to antenna array weight vector selection techniques for 60 GHz multiple-input multiple-output (MIMO)...
US-1,001,4830 DC bias circuit and the radio frequency receiver circuit using the same
The present invention presents a DC bias circuit including a first biasing circuit and a second biasing circuit. The first biasing circuit includes a first...
US-1,001,4767 Bi-directional multi-mode charge pump
Some embodiments include apparatus and methods using a charge pump coupled to a first supply power node and a second supply power node. The charge pump is...
US-1,001,4710 Foldable fabric-based packaging solution
Methods, systems, and apparatuses for a foldable fabric-based semiconductor package (FFP) that can assist with charging a secondary cell are described. An FFP...
US-1,001,4692 Apparatuses, methods, and systems with cross-coupling noise reduction
Embodiments include apparatuses, methods, and systems with cross-coupling noise reduction in circuits. In embodiments, a circuit may include a common inductor...
US-1,001,4654 Optoelectronic packaging assemblies
Optoelectronic packaging assemblies are provided that are useful for optical data, transfer In high performance computing applications, board to board in data...
US-1,001,4412 Pre-sculpting of Si fin elements prior to cladding for transistor channel applications
Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting....
US-1,001,4374 Planar heterogeneous device
In an embodiment a second semiconductor layer is transferred (e.g., using layer transfer techniques) on top of a first semiconductor layer. The second layer is...
US-1,001,4277 Single layer low cost wafer level packaging for SFF SiP
In one embodiment of the invention, a system in package (SiP) is described which includes a plurality of device components with different form factors embedded...
US-1,001,4263 Package assembly for embedded die and associated techniques and configurations
Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment,...
US-1,001,4256 Unidirectional metal on layer with ebeam
Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a layout for a...
US-1,001,4123 Overcoming variance in stacked capacitors
In one embodiment of the invention, a method of forming an energy storage device is described in which a porous structure of an electrically conductive...
US-1,001,4046 Device, system, and method of memory allocation
Device, system, and method of memory allocation. For example, an apparatus includes: a Dual In-line Memory Module (DIMM) including a plurality of Dynamic Random...
US-1,001,4036 Low power and area efficient memory receiver
An embodiment of a receiver apparatus may include high pass components to pass high frequency components of an input signal, low pass components to pass low...
US-1,001,3892 Adaptive learning environment driven by real-time identification of engagement level
Computer-readable storage media, computing devices, and methods associated with an adaptive learning environment associated with an adaptive learning...
US-1,001,3869 Effective handling of distress signals in an internet of things environment
Systems and methods may detect a condition with respect to a first device and generate a distress signal if the condition satisfies one or more safety criteria...
US-1,001,3761 Automatic orientation estimation of camera system relative to vehicle
Methods, apparatuses, and systems may provide for using the motion of a vehicle to estimate the orientation of a camera system of a vehicle relative to the...
US-1,001,3734 Programmable controller and command cache for graphics processors
In accordance with some embodiments, a command streamer may use a cache of programmable size to cache commands to improve memory bandwidth and reduce latency....
US-1,001,3731 Maximizing parallel processing in graphics processors
Methods and systems may include a computing system having a graphics processor with a three-dimensional (3D) pipeline, one or more processing units, and compute...
US-1,001,3579 Secure routing of trusted software transactions in unsecure fabric
Various configurations and methods for securing and validating trusted input output (IO) data communications within fabric interconnects of processing circuitry...
US-1,001,3392 Providing access from outside a multicore processor SoC to individually configure voltages
Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an...
US-1,001,3352 Partner-aware virtual microsectoring for sectored cache architectures
Embodiments described include systems, apparatuses, and methods using sectored dynamic random access memory (DRAM) cache. An exemplary apparatus may include at...
US-1,001,3335 Data flow analysis in processor trace logs using compiler-type information method and apparatus
A program control flow trace is obtained from a processor trace module, which may be hardware based, and is used, in combination with debug information and...
US-1,001,3326 Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was...
A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to...
US-1,001,3261 Techniques for managing or controlling computing devices
Examples are disclosed for receiving or gathering asset information associated with computing devices housed in respective decentralized locations. The gathered...
US-1,001,3260 Controls and indicators with on-screen cognitive aids
The invention relates to an applet for a mobile computing device, comprising an element to detect user input and perform appropriate associated actions, and to...
US-1,001,3254 Systems and methods for load cancelling in a processor that is connected to an external interconnect fabric
Systems and methods for load canceling in a processor that is connected to an external interconnect fabric are disclosed. As a part of a method for load...
US-1,001,3253 Method and apparatus for performing a vector bit reversal
An apparatus and method for performing a vector bit reversal. For example, one embodiment of a processor comprises: a source vector register to store a...
US-1,001,3229 Signal synchronization and latency jitter compensation for audio transmission systems
Techniques related to input and output signal synchronization and latency jitter compensation for audio systems are discussed. Such techniques may include...
US-1,001,3168 Disaggregating block storage controller stacks
Systems, apparatuses and methods may provide for communicating, by a common layer, with a local block storage system and communicating, by a subsystem layer...
US-1,001,3069 Methods and apparatus to detect vibration inducing hand gestures
Methods and apparatus to detect vibration inducing hand movements are disclosed. An example apparatus includes a sensor to detect a vibration in a hand of a...
US-1,001,3047 Operating point management in multi-core architectures
For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor...
US-1,001,3045 Apparatus, method, and system for adaptive compensation of reverse temperature dependence
Described herein are an apparatus, method, and system for adaptive compensation for reverse temperature dependence in a processor. The apparatus comprises: a...
US-1,001,3041 Directed wakeup into a secured system environment
Embodiments of processors, methods, and systems for directed wakeup into a secured system environment are disclosed. In one embodiment, a processor includes a...
US-1,001,3025 Wearable device with power state control
Embodiments of the present disclosure provide techniques and configurations for a wearable device with power state control. In one instance, the device a...
US-1,001,2784 Tiled light guide with deflection structures
Techniques and mechanisms for providing illumination of a display. In an embodiment, a light guide includes a first portion to receive light, a second portion...
US-1,000,9916 Communication device and method for processing received signals
A communication device is described comprising a receiver configured to receive a plurality of first reference signal values in a first subframe of a radio...
US-1,000,9813 Apparatus, system and method of lawful interception (LI) in a cellular network
Some demonstrative embodiments include devices, systems and/or methods of Lawful Interception (LI). For example, a device may communicate a message addressed to...
US-1,000,9725 Access point position determination by mobile devices crowd sourcing
Embodiments for performing access point position determination using crowd sourcing are generally described herein. In some embodiments, a range report request...
US-1,000,9172 Instructions processors, methods, and systems to process secure hash algorithms
A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements a.sub.i,...
US-1,000,8828 High-efficiency semiconductor laser
Embodiments of the present disclosure may relate to a hybrid silicon distributed feed-back (DFB) laser, wherein light is to propagate through the DFB laser...
US-1,000,8565 Semiconductor devices with germanium-rich active layers and doped transition layers
Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped...
US-1,000,8445 Embedded fuse with conductor backfill
Embedded fuse structures and fabrication techniques. An embedded fuse may include a non-planar conductive line having two high-z portions extending to a greater...
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