At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Inter-RAT (radio access technology) energy saving management
Systems, devices, and configurations to implement ESM (energy saving management) techniques in wireless networks are generally disclosed herein. In some...
Carrier segment support for wireless networks
Briefly, in accordance with one or more embodiments, a base transceiver station such as an Enhanced Node B allocates a first bandwidth for operation with a...
Extended access barring
A system and method for authorizing access to a transmission station for a mobile device is disclosed. The mobile device can receive device extended access...
User equipment and method for enhanced uplink power control
Embodiments of user equipment and methods for improved uplink transmission power management and scheduling, are generally described herein. For example, in an...
DRX operation for UL/DL reconfiguration
In embodiments, apparatuses, methods, and storage media may be described for identifying subframes in a radio frame on which a UE may receive a Physical...
Depth buffer compression for stochastic motion blur rasterization
A depth buffer compression scheme uses bilinear patches as a predictor for depth. The scheme targets compression of scenes rendered with stochastic blur...
Techniques for mobile augmented reality applications
Techniques are disclosed that involve mobile augmented reality (MAR) applications in which users (e.g., players) may experience augmented reality. Further, the...
Cloud data storage location monitoring
Technologies for monitoring data storage location for cloud data include a cloud monitoring server configured to communicate with one or more cloud customer...
Providing regulatory information to a group owner for channel selection in
a wireless peer-to-peer network
In a wireless peer-to-peer (P2P) network or group, regulatory information may be provided from a P2P client device to a P2P group owner device for use in...
Secure and automatic connection to wireless network
Described herein are systems, methods, and apparatus for automatically establishing secure connections to wireless networks using a wireless local area network...
Techniques for guaranteeing bandwidth with aggregate traffic
Methods, systems, and apparatus guarantee bandwidth for a network transaction. A network is logically organized as a tree having a plurality of nodes. Each node...
Transition time measurement of PAM4 transmitters
Methods, apparatus and systems for measuring signal transition times for a four-level pulse modulated amplitude (PAM4) transmitter. During a test procedure, a...
Technologies for configuring transmitter equalization in a communication
Technologies for transmitter equalization in a communication system include reading local transmitter equalization settings from a transmitter equalization...
Successive interference cancellation system and method for MIMO horizontal
encoding and decoding
A method and system for receiving and decoding horizontally encoded MIMO-OFDM transmissions with improved efficiency. In one embodiment, MIMO decoding is...
Enhanced node B and methods for network assisted interference cancellation
with reduced signaling
Embodiments of an enhanced node B (eNB) and methods for network-assisted interference cancellation with reduced signaling in a 3GPP LTE network are generally...
Apparatus and a method for determining information on an amplitude error
of a transmit signal
An apparatus for determining information on an amplitude error of a transmit signal includes at least one transmit path module, at least one feedback receive...
Measuring bit error rate during runtime of a receiver circuit
In one embodiment, a receiver includes: a data path having a first slicer to receive and sample an incoming analog signal and to determine a bit level for the...
Mobile unit having internet protocol functionality
A mobile unit includes a handset and a removable storage module having a unique storage module identity, for storing information specific to a user, including...
Secret operations using reconfigurable logics
An integrated circuit includes a programmable logic device and optionally a control circuit coupled to the programmable logic device (PLD). The control circuit...
Distributed power delivery scheme for on-die voltage scaling
A high-speed low dropout (HS-LDO) voltage regulation circuit suitable to enable a power gate unit to produce a variable voltage signal based on the load of a...
Inclined photonic chip package for integrated optical transceivers and
optical touchscreen assemblies
An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An...
Techniques for forming non-planar germanium quantum well devices
Techniques are disclosed for forming a non-planar germanium quantum well structure. In particular, the quantum well structure can be implemented with group IV...
Capping poly channel pillars in stacked circuits
A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition...
Semiconductor chip stacking assemblies
Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second...
Interlayer communications for 3D integrated circuit stack
Some embodiments provide capacitive AC coupling inter-layer communications for 3D stacked modules.
Chip interposer, semiconductor device, and method for manufacturing a
A chip interposer may include: a first interconnect level including a first pad; and a second interconnect level including a second pad, wherein the second pad...
Methods of connecting a first electronic package to a second electronic
A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within...
Low power transient voltage collapse apparatus and method for a memory
Described is an apparatus for memory write assist which consumes low power during write assist operation. The apparatus comprises: a power supply node; a device...
Front to back compositing
In one embodiment, pixels that cannot change their color due to the alpha blend mode and the color already stored in a render target are detected. For example,...
Hybrid rendering systems and methods
Embodiments of a system and method for enhanced graphics rendering performance in a hybrid computer system are generally described herein. In some embodiments,...
Image capture feedback
Embodiments for image capture feedback are disclosed. In some embodiments, a computing system may receive a first image from an image capture device and...
Handwritten signature detection, validation, and confirmation
Technologies may provide for detecting, validating, or confirming the validity of a handwritten signature. A logic architecture may be employed to detect a...
Architected protocol for changing link operating mode
In one embodiment, a device having a link training state machine including a reconfiguration logic to perform a dynamic link reconfiguration of a physical link...
Adaptive interrupt moderation
Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the...
De-interleaving on an as-needed basis
One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved...
Method, apparatus and system for measuring latency in a physical unit of a
In an embodiment, an apparatus includes a counter to count between a start value and an end value according to a local clock signal, a first register to store...
Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
Page miss handler including wear leveling logic
Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices....
Signature based hit-predicting cache
An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed...
Live error recovery
A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is...
Error correction in solid state drives (SSD)
A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less...
Using dark bits to reduce physical unclonable function (PUF) error rate
without storing dark bits location
Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key...
Method and system for work partitioning between processors with work
A method according to one embodiment includes the operations of loading binary code comprising a top level task into memory on a first processor, the top level...
Method for reducing platform boot times by providing lazy input/output
Methods, systems and computer program products are disclosed for enhanced system boot processing that is faster to launch an operating system, as certain...
Critical section detection and prediction mechanism for hardware lock
A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock...
Efficient implementation of RSA using GPU/CPU architecture
Various embodiments are directed to a heterogeneous processor architecture comprised of a CPU and a GPU on the same processor die. The heterogeneous processor...
Real time instruction trace processors, methods, and systems
A method of an aspect includes generating real time instruction trace (RTIT) packets for a first logical processor of a processor. The RTIT packets indicate a...
Performing a cyclic redundancy checksum operation responsive to a
In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data...
System for portable tangible interaction
Embodiments of the invention describe a system utilizing at least one camera and a display to create an object and context aware system. Embodiments of the...
Multi-touch interface schemes
Systems, devices and methods are described including using a Human Interface Device (HID) source device to configure a HID sink device to provide interface data...