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Patent # Description
US-9,294,222 Variable rate coding for forward and reverse link
A technique for encoding a signal used in a digital communication system in which individual traffic channel data rates may be adapted to specific channel...
US-9,294,213 Packet data network connections for multi priority wireless devices
A device and method for forming a packet data network (PDN) connection at a dual access priority mode configured user equipment (UE) is disclosed. The method...
US-9,294,145 Methods and arrangements for very large bandwidth operations
Logic may determine a first frame comprising a hopping pattern value and a target hopping time (THT). The hopping pattern may indicate a pattern of channels to...
US-9,294,140 Radio frequency interference mitigation
A computing device including a wireless communication system is provided herein. The computing device includes a plurality of antennas coupled to the wireless...
US-9,294,123 Apparatus and method to accelerate compression and decompression operations
Methods and apparatuses relating to an instruction to decode encoded information of a compression scheme are described. In one embodiment, a processor includes...
US-9,294,104 Phase-locked loop circuit with improved performance
A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency...
US-9,294,035 Multigate resonant channel transistor
An embodiment includes an oscillator comprising an amplifier formed on a substrate; a multiple gate resonant channel array, formed on the substrate, including:...
US-9,293,809 Forty-five degree dual broad band base station antenna
The present invention relates to a multiband antenna specifically adapted for use with a Base Station Antenna ("BSA"). The present invention provides narrow...
US-9,293,798 Crosstalk cancellation and/or reduction
Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged...
US-9,293,579 Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
US-9,293,560 Vertical nanowire transistor with axially engineered semiconductor and gate metallization
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In...
US-9,293,546 Vertical tunneling negative differential resistance devices
The present disclosure relates to the fabrication of microelectronic devices having at least one negative differential resistance device formed therein. In at...
US-9,293,428 Low profile heat spreader and methods
Embodiments of semiconductor chip assemblies, and methods are shown that include adhesive thermal interface materials between a heat spreader and a...
US-9,293,426 Land side and die side cavities to reduce package Z-height
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die...
US-9,293,423 Workpiece with semiconductor chips, semiconductor device and method for producing a workpiece with...
A workpiece has at least two semiconductor chips, each semiconductor chip having a first main surface, which is at least partially exposed, and a second main...
US-9,293,224 Double data rate in parallel testing
Briefly, in accordance with one or more embodiments, an apparatus to test a semiconductor device comprises a controller configured to perform one or more tests...
US-9,293,202 Path isolation in a memory device
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one...
US-9,292,927 Adaptive support windows for stereoscopic image correlation
Systems, apparatus and methods are described related to adaptive support windows for stereoscopic image correlation.
US-9,292,900 Partition-free multi-socket memory system architecture
A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput...
US-9,292,898 Conditional end of thread mechanism
A graphics processing unit, method, computer readable media, and system are described herein. The graphics processing unit includes at least one execution unit,...
US-9,292,864 Wireless communication device and methods for synched distributed advertisement for device-to-device discovery
Examples of a communication device and methods for synched distributed advertisement for device-to-device are generally described herein. In some embodiments, a...
US-9,292,841 System and method for transferring playlists
A method, computer program product and computing device for selecting at least one playlist for transfer, the at least one playlist being stored on a first...
US-9,292,753 Parallel face detection and tracking system
The present disclosure is directed to a parallel face detection and tracking system. In general, embodiments consistent with the present disclosure may be...
US-9,292,731 Gesture-based signature authentication
Embodiments of the invention are generally directed to systems, methods, devices, and machine-readable mediums for implementing gesture-based signature...
US-9,292,713 Tiered access to on chip features
In accordance with some embodiments, multiple blind debug passwords are provided. Each of a plurality of interested entities may have its own password and each...
US-9,292,683 Computing device security
Techniques for providing security for a computing device are described herein. In one example, a maintenance issue for the computing device is detected....
US-9,292,679 Regulating access to and protecting portions of applications of virtual machines
Embodiments of apparatus, computer-implemented methods, systems, and computer-readable media are described herein for a virtual machine manager, wherein the...
US-9,292,548 Digest generation
In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other...
US-9,292,476 Fourier transform computation for distributed processing environments
Fourier transform computation for distributed processing environments is disclosed. Example methods disclosed herein to compute a Fourier transform of an input...
US-9,292,468 Performing frequency coordination in a multiprocessor system based on response timing optimization
In an embodiment, a processor includes a core to execute instructions and a logic to receive memory access requests from the core and to route the memory access...
US-9,292,465 Dynamic link width adjustment
Embodiments help dynamically configure the width of PCIe links and also determine how to best configure the appropriate link width. This helps avoid situations...
US-9,292,463 Communication of device presence between boot routine and operating system
Various embodiments are directed to creating multiple device blocks associated with hardware devices, arranging the device blocks in an order indicative of...
US-9,292,449 Cache memory data compression and decompression
A cache memory data compression and decompression technique is described. A processor device includes a memory controller unit (MCU) coupled to a main memory...
US-9,292,426 Fast exit from DRAM self-refresh
Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low...
US-9,292,384 Storage systems with adaptive erasure code generation
Apparatuses, methods and storage medium associated with generating erasure codes for data to be stored in a storage system. In embodiments, a method may include...
US-9,292,379 Apparatus and method to manage high capacity storage devices
Apparatus, systems, and methods to manage high capacity memory devices are described. In one example, a controller comprises logic to receive a write operation...
US-9,292,362 Method and apparatus to protect a processor against excessive power usage
In an embodiment, a processor includes at least a first core. The first core includes execution logic to execute operations, and a first event counter to...
US-9,292,359 System and method for memory management
A system and method for automatic memory management of a shared memory during parallel processing of a web application. The system includes a computing system...
US-9,292,297 Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction
According to one embodiment, a processor includes an instruction decoder to receive an instruction to process a multiply-accumulate operation, the instruction...
US-9,292,294 Detection of memory address aliasing and violations of data dependency relationships
Method and apparatus to efficiently detect violations of data dependency relationships. A memory address associated with a computer instruction may be obtained....
US-9,292,288 Systems and methods for flag tracking in move elimination operations
Systems and methods for flag tracking in data manipulation operations involving move elimination. An example processing system comprises a first data structure...
US-9,292,283 Method for fast large-integer arithmetic on IA processors
Methods, systems, and apparatuses are disclosed for implementing fast large-integer arithmetic within an integrated circuit, such as on IA (Intel Architecture)...
US-9,292,255 Multi-stage crest factor reduction (CFR) for multi-channel multi-standard radio
Multi-stage crest factor reduction (CFR) techniques are provided for multi-channel multi-standard radio (MSR). A multi-stage crest factor reduction method...
US-9,292,250 Devices, methods, and systems for providing interactivity with digital signs
A device, method, and system for providing interactivity with a digital sign includes an interactive digital sign configured to display information in response...
US-9,292,221 Bi-directional copying of register content into shadow registers
Embodiments of the present disclosure describe a processor, which may include copy circuitry coupled to a shadow register file and a control register. The copy...
US-9,292,213 Maintaining at least one journal and/or at least one data structure by circuitry
An embodiment may include circuitry to perform option (a) and/or option (b). In option (a), the circuitry may maintain a journal to record information that is...
US-9,292,114 Dual touch surface multiple function input device
For one disclosed embodiment, an apparatus includes a first housing and a touch input device supported by the first housing. The touch input device includes a...
US-9,292,103 Gesture pre-processing of video stream using skintone detection
Techniques are disclosed for processing a video stream to reduce platform power by employing a stepped and distributed pipeline process, wherein CPU-intensive...
US-9,292,084 Control systems and methods for head-mounted information systems
A head-mounted information system is provided, the head-mounted information system comprising a frame configured to be mounted on a head of a user, a display...
US-9,292,076 Fast recalibration circuitry for input/output (IO) compensation finite state machine power-down-exit
Fast recalibration circuitry for input/output (IO) compensation finite state machine power-down exit is described. The fast recalibration circuitry includes a...
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