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Patent # Description
US-1,028,4346 Systems and methods for signal classification
This disclosure describes systems, and methods related to signal classification in a wireless communication network. A first computing device comprising one or...
US-1,028,4332 Spur cancelation using inverse spur injection
A spur cancelation system includes error circuitry, inverse spur circuitry, and injection circuitry. The error circuitry is configured to generate an error...
US-1,028,4275 Single user and multiuser multiple-input and multiple-output beamforming
This disclosure describes systems, methods, and devices related to multiple-input and multiple-output (MIMO) beamforming. A device may determine one or more...
US-1,028,4241 Receivers and methods for reducing an interference component in a receive signal
A receiver for reducing an interference component in a receive signal is provided. The interference component is caused by a first interferer emitting payload...
US-1,028,4210 Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO)
Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). In...
US-1,028,4199 Voltage tolerant termination presence detection
Apparatuses and methods associated with voltage tolerant termination presence detection for universal serial bus type-C connectors are disclosed herein. In...
US-1,028,4166 Transmitter matching network using a transformer
An apparatus for a network matching switch is provided. The apparatus includes a primary winding, a first secondary winding, a second secondary winding and a...
US-1,028,3850 Wireless wearable devices having self-steering antennas
Wireless wearable devices having self-steering antennas are disclosed. A disclosed example wearable device includes an antenna to be communicatively coupled to...
US-1,028,3640 Source/drain contacts for non-planar transistors
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate...
US-1,028,3589 Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device...
US-1,028,3453 Interconnect routing configurations and associated techniques
Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus...
US-1,028,2982 Aggregated analytics for intelligent transportation systems
Various systems and methods for collecting and generating analytics of data from motor vehicle safety and operation systems are disclosed herein. In one...
US-1,028,2965 Synthetic jet delivering controlled flow to sensor system
Techniques are disclosed for using synthetic jet technology as an air delivery device for sensing applications. In particular, a synthetic jet device is used to...
US-1,028,2890 Method and apparatus for the proper ordering and enumeration of multiple successive ray-surface intersections...
An apparatus and method are described for performing a distance test in a ray tracing system. For example, one embodiment of a graphics processing apparatus...
US-1,028,2886 Wearable device providing micro-visualization
Embodiments are generally directed to a wearable device providing micro-visualization. A wearable electronic device may include a processor to process data; an...
US-1,028,2812 Page faulting and selective preemption
One embodiment provides for a parallel processor comprising a processing array within the parallel processor, the processing array including multiple compute...
US-1,028,2811 Apparatus and method for managing data bias in a graphics processing architecture
An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, one embodiment of an apparatus comprises: a...
US-1,028,2808 Hierarchical lossless compression and null data support
Described herein are computer graphics technologies to facilitate effective and efficient memory handling for blocks of memory including texture maps. More...
US-1,028,2804 Facilitating configuration of computing engines based on runtime workload measurements at computing devices
A mechanism is described for facilitating configuration of computing engines based on runtime workload measurements at computing devices. A method of...
US-1,028,2641 Technologies for classification using sparse coding in real time
Technologies for classification using sparse coding are disclosed. A compute device may include a pattern-matching accelerator, which may be able to determine...
US-1,028,2538 Technologies for providing hardware subscription models using pre-boot update mechanism
Technologies to enable, disable and control hardware subscription features. Computing devices communicate over a network to a subscription server to provide...
US-1,028,2465 Systems, apparatuses, and methods for deep learning of feature detectors with sparse coding
Detailed herein are embodiments of systems, methods, and apparatuses to be used for feature searching using an entry-based searching structure.
US-1,028,2344 Sensor bus interface for electronic devices
In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the...
US-1,028,2341 Method, apparatus and system for configuring a protocol stack of an integrated circuit chip
Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is...
US-1,028,2323 Memory channel that supports near memory and far memory access
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic...
US-1,028,2322 Memory channel that supports near memory and far memory access
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic...
US-1,028,2306 Supporting secure memory intent
A processor for supporting secure memory intent is disclosed. The processor of the disclosure includes a memory execution unit to access memory and a processor...
US-1,028,2300 Accessing physical memory from a CPU or processing element in a high performance manner
A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor...
US-1,028,2296 Zeroing a cache line
Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and...
US-1,028,2287 Interleaved direct access mode in byte addressible memory and related devices and systems
Memory devices and systems having direct access mode (DAM) space allocation across interleaved non-volatile memory (NVM) modules, as well as methods of...
US-1,028,2227 Efficient preemption for graphics processors
Systems and methods may provide for inserting one or more preemption instructions while compiling a computer program. The one or more preemption instructions...
US-1,028,2204 Systems, apparatuses, and methods for strided load
Systems, methods, and apparatuses for strided loads are described. In an embodiment, an instruction to include at least an opcode, a field for at least two...
US-1,028,2182 Technologies for translation cache management in binary translation systems
Technologies for optimized binary translation include a computing device that determines a cost-benefit metric associated with each translated code block of a...
US-1,028,2170 Method for a stage optimized high speed adder
A method for fast parallel adder processing. The method includes receiving parallel inputs from a communications path, wherein each input comprises one bit,...
US-1,028,2122 Methods and systems of a memory controller for hierarchical immutable content-addressable memory processor
Improved memory management is provided according to a Hierarchical Immutable Content Addressable Memory Processor (HICAMP) architecture. In HICAMP, physical...
US-1,028,2091 Bi-stable display based off-screen keyboard
A display based keyboard is described herein. The display based keyboard includes a bi-stable segmented-based display, a master controller, and a display...
US-1,028,1975 Processor having accelerated user responsiveness in constrained environment
In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller...
US-1,028,1521 System for thermal management of device under test (DUT)
Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface...
US-1,028,1322 Low power, high resolution solid state LIDAR circuit having a modulator to modulate a bit sequence onto a...
An optical circuit includes solid state photonics. The optical circuit includes a phased array of solid state waveguides that perform beamsteering on an optical...
US-D847,810 Computer notebook
US-1,027,8318 Method of assembling an electronic component using a probe having a fluid thereon
A method of assembly comprising providing an assembly probe, the assembly probe having an end coupling face; providing a droplet of fluid on the end coupling...
US-1,027,8302 Device, system and method for providing zone-based configuration of socket structures
Techniques and mechanisms for providing socket connection to a substrate. In an embodiment, a socket device includes a first socket body portion that is to...
US-1,027,8292 Method for orienting solder balls on a BGA device
A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR)...
US-1,027,8121 Blacklisting techniques for detected set event evaluation
Blacklisting techniques for detected set event evaluation are described. In one embodiment, for example, user equipment (UE) may comprise at least one radio...
US-1,027,8057 Network assisted device to device discovery
Technology for a user equipment (UE) operable to perform device to device (D2D) discovery in a wireless network is described. The UE can decode D2D discovery...
US-1,027,8056 Wireless communication networks with probe response
In one example, a method for providing probe responses in a wireless communication network includes determining, in response to a broadcast probe request from a...
US-1,027,8044 Systems and methods for transmitting and managing communication on dedicated short-range communication channels
The present disclosure relates to computer-implemented systems and methods for transmitting and receiving audio and video data. A method may include receiving,...
US-1,027,8025 Device clustering for enhanced location services
The apparatus of a first wireless communication device includes memory comprising instructions and processing circuitry coupled to the memory. The processing...
US-1,027,7932 Crowdsourced voting via interaction between crowdsource client and crowdsourced client interface
Systems, apparatuses, and methods may provide for technology to conduct contemporaneous crowd-sourced voting via interaction between a client and a client...
US-1,027,7908 Inter-layer sample adaptive filter parameters re-use for scalable video coding
Described herein are techniques related to re-use of filter parameters, and particularly Sample Adaptive Offset (SAO) parameters, of a lower-layer bitstream or...
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