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Patent # Description
US-1,041,1001 Dynamic random access memory (DRAM) mounts
Donut-shaped Dynamic Random Access Memory (DRAM) includes a hole that fits around a processor, such that the DRAM and the processor are adjacent to one another...
US-1,041,1000 Microelectronic package with illuminated backside exterior
A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package...
US-1,041,0983 Microelectronic devices designed with high frequency communication devices including compound semiconductor...
Embodiments of the invention include a microelectronic device that includes an overmolded component having a first die with a silicon based substrate. A second...
US-1,041,0940 Semiconductor package with cavity
An embodiment includes a method comprising: coupling a sacrificial material to a substrate; forming a first dielectric material adjacent the sacrificial...
US-1,041,0939 Package power delivery using plane and shaped vias
Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first...
US-1,041,0867 Confined and scalable helmet
An embodiment includes a system comprising: a first gate and a first contact that correspond to a transistor and are on a first fin; a second gate and a second...
US-1,041,0699 Multi-bit pulsed latch including serial scan chain
Some embodiments include apparatuses having a plurality of latches, each of the latches including a first input node to receive first information during a first...
US-1,041,0590 Facilitating chromatic adaptation of display contents at computing devices based on chromatic monitoring of...
A mechanism is described for facilitating chromatic adaptation of display contents based on chromatic monitoring of environmental light at computing devices. A...
US-1,041,0560 Display controller testing through high speed communications switch
Embodiments are generally directed to display controller testing through a high speed communications switch. An embodiment of an apparatus includes a display...
US-1,041,0399 Determining n-dimensional Euclidian distance in graphics for improved texture sampling and level of detail
Methods and apparatus relating to techniques for. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to determine a...
US-1,041,0311 Method and apparatus for efficient submission of workload to a high performance graphics sub-system
Embodiments provide for an apparatus comprising a graphics processing subsystem including one or more graphics engines and a graphics scheduler to schedule a...
US-1,041,0211 Virtual POS terminal method and apparatus
Methods, systems, and storage media are described for processing point of sale (POS) transactions. In embodiments, a computing device may receive a transaction...
US-1,041,0129 User pattern recognition and prediction system for wearables
One embodiment provides an apparatus. The apparatus includes a companion device. The companion device includes pattern recognition logic to construct a...
US-1,041,0115 Autonomous machines through cloud, error corrections, and predictions
A mechanism is described for facilitating smart collection of data and smart management of autonomous machines. A method of embodiments, as described herein,...
US-1,041,0098 Compute optimizations for neural networks
One embodiment provides for a compute apparatus to perform machine learning operations, the apparatus comprising a decode unit to decode a single instruction...
US-1,041,0081 Method and apparatus for a high throughput rasterizer
An apparatus and method are described for a high throughput rasterizer. For example, one embodiment of an apparatus comprises: block selection logic to select a...
US-1,041,0045 Automated facial recognition systems and methods
A facial recognition system determines an estimated biological age of a subject in a current image. A facial recognition controller identifies the subject in...
US-1,040,9998 Providing intrusion detection, monitoring and protection in a system
In an embodiment, a system includes a processor with at least one core to execute an application to provide intrusion detection and protection, a radar sensor...
US-1,040,9974 Technologies for authorizing a user to a protected system
Technologies for user authorization include a compute device configured to determine one or more physical attributes of a non-electronic physical object and...
US-1,040,9962 System and method for controlling access to protected content
A receiver includes a first interface to receive content, a second interface to be coupled to a device, and a processor to determine whether the device is a...
US-1,040,9763 Apparatus and method for efficiently implementing a processor pipeline
Various different embodiments of the invention are described including: (1) a method and apparatus for intelligently allocating threads within a binary...
US-1,040,9737 Apparatus, system, and method for positionally aware device management bus address assignment
Provided are apparatus, system, and method for positionally aware device management bus address assignment. A presence of a plurality of storage devices is...
US-1,040,9727 System, apparatus and method for selective enabling of locality-based instruction handling
In an embodiment, a processor includes a sparse access buffer having a plurality of entries each to store for a memory access instruction to a particular...
US-1,040,9614 Instructions having support for floating point and integer data types in the same register
One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising instruction decode logic to decode a...
US-1,040,9613 Processing devices to perform a key value lookup instruction
Single Instruction, Multiple Data (SIMD) technologies are described. A method of performing a key value lookup instruction may include storing a vector of keys...
US-1,040,9612 Apparatus and method for transactional memory and lock elision including an abort instruction to abort...
An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code...
US-1,040,9611 Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or...
An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code...
US-1,040,9603 Processors, methods, systems, and instructions to check and store indications of whether memory addresses are...
A processor of an aspect includes a decode unit to decode an instruction. The instruction is to indicate a source memory address information, and is to indicate...
US-1,040,9601 Apparatus and method for loop flattening and reduction in a single instruction multiple data (SIMD) pipeline
An apparatus and method for loop flattening and reduction in a SIMD pipeline including broadcast, move, and reduction instructions. For example, one embodiment...
US-1,040,9597 Memory management in secure enclaves
Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution...
US-1,040,9571 Apparatus and method for efficiently accessing memory when performing a horizontal data reduction
Apparatus and method for optimizing shader execution. For example, one embodiment of a graphics processing apparatus comprises: a plurality of execution units...
US-1,040,9500 Multiple indirection granularities for mass storage devices
One embodiment provides a memory controller. The memory controller includes logical block address (LBA) section defining logic to define a plurality of LBA...
US-1,040,9360 Distribution of tasks among asymmetric processing elements
Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate...
US-1,040,9346 Controlling power delivery to a processor via a bypass
In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear...
US-1,040,9319 System, apparatus and method for providing a local clock signal for a memory array
In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a...
US-1,040,9152 Pattern decomposition lithography techniques
Techniques are disclosed for realizing a two-dimensional target lithography feature/pattern by decomposing (splitting) it into multiple unidirectional target...
US-1,040,8930 Beamforming training using echoes of an omnidirectional pulse
Methods and devices for estimating an angle between a transmitter and a receiver for beamforming are provided. A method includes, with an antenna element in a...
US-1,040,8929 Non-synchronized RF ranging
Various systems and methods for determining a distance between a master device and a slave device based, at least in part, on a received signal strength and...
US-1,040,8860 Interconnection system with flexible pins
An embodiment includes a system comprising: a polymer substrate including a plurality of voids; and a plurality of metal pins; wherein a first pin, included...
US-1,040,5420 Gullwing PCB structure to enable high frequency operation
Embodiments include devices and method related to a foldable printed circuit board that may be used in SSD applications. One embodiment relates to a foldable...
US-1,040,5371 Enhanced node B, user equipment and methods for discontinuous reception in inter-eNB carrier aggregation
Embodiments of user equipment (UE) and methods for enhanced discontinuous reception (DRX) operations for inter eNB carrier aggregation (CA) in an LTE network...
US-1,040,5333 Communication device and method for receiving signals in a frequency range
A communication terminal is described comprising a first transceiver configured for communication according to a first radio access technology and a second...
US-1,040,5331 Systems, methods and devices for radio access technology coordination
User equipment and base stations can enable access to secondary radio access technology (S-RAT), a cross radio access technology (RAT) scheduling between a...
US-1,040,5330 System and method for dynamic marking for internet protocol bearer splitting
A User Equipment (UE), an evolved Node B (eNB), or a PDN Gateway (PGW) comprising a processing circuitry to comprise a user-plane multi-link data convergence...
US-1,040,5319 Techniques to enhance wireless personal area network performance under interference conditions
An apparatus to manage wireless communications may include an interface component to monitor channel load over a multiplicity of communications channels in an...
US-1,040,5311 Scheduling trigger frames in a high efficiency wireless local-area network
Apparatuses, computer readable media, and methods for scheduling trigger frames in a high-efficiency wireless (HEW) local-area network are disclosed. An...
US-1,040,5310 Time division duplex (TDD) uplink downlink (UL-DL) reconfiguration
An eNodeB operable to perform Enhanced Interference Mitigation & Traffic Adaptation (eIMTA) is disclosed. The eNodeB can select a radio network temporary...
US-1,040,5273 Access point (AP), station (STA) and method for subcarrier scaling
Embodiments of an access point (AP), station (STA) and method for subcarrier scaling are generally described herein. The AP may transmit a high efficiency (HE)...
US-1,040,5249 Device and method for radio cell selection
This disclosure relates to a mobile device, comprising: a receiver configured to receive a radio signal comprising transmissions from a plurality of radio...
US-1,040,5211 High efficiency distributed device-to-device (D2D) channel access
Techniques for facilitating device-to-device (D2D) communications using a high efficiency distributed channel access scheme are generally described herein. In...
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