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Optimizing security bits in a media access control (MAC) header
A method of retrieving security information in a media access control (MAC) header by a wireless station may include receiving a data unit, such as a protocol...
Method for signaling information by modifying modulation constellations
Methods and systems for communicating in a wireless network may distinguish different types of packet structures by modifying the phase of a modulation...
Coordinated interference mitigation and cancelation
A method includes receiving at user equipment an indication of a subset of scheduling constraints for interference mitigation and cancelation and performing...
Determining proximity of user equipment for device-to-device communication
Embodiments of apparatus, packages, computer-implemented methods, systems, devices, and computer-readable media (transitory and non-transitory) are described...
Error detecting and correcting structured light patterns
Techniques are disclosed for detecting image depth in three-dimensional (3-D) surface imaging. The disclosed techniques can be used, for example, to provide...
Method, apparatus and system of recovering an operating system on a
portable communication device
A device, method and system for recovering an operating system may comprise a near field communication module; a high speed wireless communication module; and a...
Adaptive clock spreading for platform RFI mitigation
An apparatus, system, and method, the method including receiving clock frequency parameter information for at least one clock source; receiving radio parameter...
Spin transfer torque based memory elements for programmable device arrays
Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use...
Localized high density substrate routing
Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus...
Debond interconnect structures
The present subject matter relates to the field of fabricating microelectronic devices. In at least one embodiment, the present subject matter relates to...
Through silicon via guard ring
The present disclosure relates to forming a plurality of through silicon vias guard rings proximate the scribes streets of a microelectronic device wafer. The...
Chemically altered carbosilanes for pore sealing applications
A method including forming a dielectric material including a surface porosity on a circuit substrate including a plurality of devices; chemically modifying a...
Patterning of vertical nanowire transistor channel and gate with directed
Directed self-assembly (DSA) material, or di-block co-polymer, to pattern features that ultimately define a channel region a gate electrode of a vertical...
Narrow-gap flip chip underfill composition
An underfill composition comprises a curable resin, a plurality of filler particles loaded within the resin, the filler particles comprising at least 50 weight...
Non-contact power transmission apparatus
A non-contact power transmission apparatus accurately determines the kind of object that is placed on the charging deck of the non-contact power transmission...
System and method for intelligently flushing data from a processor into a
A system and method are described for intelligently flushing data from a processor cache. For example, a system according to one embodiment of the invention...
Techniques for determining victim row addresses in a volatile memory
Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and...
Memory refresh management
Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory...
Bit cell write-assistance
Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and Bit nodes of a bit cell prior to a write operation....
Computer graphics processor and method for rendering a three-dimensional
image on a display screen
A computer graphics processor and a method for rendering a three-dimensional image on a display screen. The computer graphics processor comprises a rasterizer...
Techniques for managing system power using deferred graphics rendering
An apparatus may include a memory to store one or more graphics rendering commands in a queue after generation. The apparatus may also include a processor...
Dynamically rebalancing graphics processor resources
According to some embodiments, performance bottlenecks that arise in particular resources within a graphic processor unit may be alleviated by dynamically...
Smile detection techniques
Techniques are disclosed that involve the detection of smiles from images. Such techniques may employ local-binary pattern (LBP) features and/or multi-layer...
Secure access enforcement proxy
Efficient architecture for a secure access enforcement proxy is described. The proxy interfaces with multiple subsystems and multiple shared resources. The...
Photolithography mask synthesis for spacer patterning
Photolithography mask synthesis is disclosed for spacer patterning masks. In one example, backbone features are extracted from a target layout of a mask design....
Child state pre-fetch in NFAs
Disclosed is a method and apparatus for pre-fetching child states in an NFA cell array. A pre-fetch depth value is determined for each transition in an NFA...
Reconfigurable variable length fir filters for optimizing performance of
The invention addresses the problem of parameter optimization for best filter performance and, in particular, the influence from the requirements on radio or...
Controlling devices via advance notice signaling
Generally this disclosure describes methods and systems for controlling device operation in a processing system. A method may include receiving information...
Configuration of data strobes
Disclosed embodiments may include a circuit having a plurality of data terminals, no more than two pairs of differential data strobe terminals associated with...
Dram compression scheme to reduce power consumption in motion compensation
and display refresh
Systems and methods of operating a memory controller may provide for receiving a write request from a motion compensation module, wherein the write request...
Method, system and apparatus for region access control
Techniques and mechanisms for providing access to a storage device of a computer platform. In an embodiment, an agent executing on the platform may be...
Low overhead paged memory runtime protection
Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical...
Snoop filter having centralized translation circuitry and shadow tag array
A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing...
Fast mechanism for accessing 2n.+-.1 interleaved memory system
A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2.sup.n+1) or (2.sup.n-1), n...
Background reordering--a preventive wear-out control mechanism with
Embodiments of the present disclosure describe background reordering techniques and configurations to prevent wear-out of an integrated circuit device such as a...
Adaptive moving read references for memory cells
Examples are disclosed for generating or providing a moving read reference (MRR) table for recovering from a read error of one or more memory cells of a...
Apparatus and method for vectorization with speculation support
An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises:...
Application scheduling in heterogeneous multiprocessor computing platform
based on a ratio of predicted...
Methods and apparatus to schedule applications in heterogeneous multiprocessor computing platforms are described. In one embodiment, information regarding...
Instruction and logic to test transactional execution status
Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start...
Scheduling thread execution based on thread affinity
In accordance with some embodiments, spatial and temporal locality between threads executing on graphics processing units may be analyzed and tracked in order...
Processor extensions for execution of secure embedded containers
Methods and apparatus relating to processor extensions for execution of secure embedded containers are described. In an embodiment, a scalable solution for...
DFA compression and execution
A character class (CCL) memory containing simple CCLs represented by encoding contained symbols or minimum and maximum symbols of a range, complex CCLs...
Method and apparatus for agent interfacing with pipeline backbone to
locally handle transactions while obeying...
In accordance with embodiments disclosed herein, there are provided methods, systems, and apparatuses for enabling an agent interfacing with a pipelined...
Instruction and logic for boyer-moore search of text strings
Instructions and logic provide extended vector suffix comparisons for Boyer-Moore searches. Some embodiments, responsive to an instruction specifying: a pattern...
Method and apparatus for performing logical compare operations
A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In...
Vector and scalar based modular exponentiation
An embodiment includes a method for computing operations, such as modular exponentiation, using a mix of vector and scalar instructions to accelerate various...
Connecting mobile devices, internet-connected hosts, and cloud services
Applications are downloaded to a device from a cloud-based service by establishing trust with between the device and a host system. The host system and the...
Methods and systems to vectorize scalar computer program loops having
Methods and systems to convert scalar computer program loops having loop carried dependences to vector computer program loops are disclosed. One example method...
Enforcing a power consumption duty cycle in a processor
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently...
Techniques and system for managing platform temperature
In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a...