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Patent # Description
US-9,337,874 High-speed digital signal processing systems
Apparatus and method to provide a high speed digital signal processor may implemented in a substantially all digital transmitter designs. In an embodiment,...
US-9,337,734 DC-DC converter for envelope tracking
Embodiments provide a DC-DC converter (DC-DC=direct current to direct current) for envelope tracking. The DC-DC converter includes a digital control stage and a...
US-9,337,661 Power management system and method
An apparatus including a storage area to store instructions and a controller to control power in a first device based on the instructions. In operation, the...
US-9,337,628 Ionic cooling assembly for electronic device
In one embodiment an ionic airflow system comprises an anode, a cathode platform having an elongated surface, and a first ultrasonic transducer to direct...
US-9,337,521 Crosstalk reduction in signal lines by crosstalk introduction
A circuit component is described herein. The circuit component includes a first signal line to propagate in a first direction and a second signal line to...
US-9,337,336 Replacement metal gates to enhance tranistor strain
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
US-9,337,307 Method for fabricating transistor with thinned channel
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The...
US-9,337,291 Deep gate-all-around semiconductor device having germanium or group III-V active layer
Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes...
US-9,336,873 Apparatus for time domain offset cancellation to improve sensing margin resistive memories
Described are apparatuses for time domain offset cancellation. One example of the apparatus includes: a variable resistance memory cell; a reference resistive...
US-9,336,561 Color buffer caching
A color buffer cache may be implemented in a way that reduces memory bandwidth. In one embodiment this may be done by determining whether a corresponding tile...
US-9,336,460 Adaptive motion instability detection in video
One or more apparatus and method for adaptively detecting motion instability in video. In embodiments, video stabilization is predicated on adaptive detection...
US-9,336,357 Secure access management of devices
Systems and methods may provide implementing one or more device locking procedures to block access to a device. In one example, the method may include receiving...
US-9,336,175 Utilization-aware low-overhead link-width modulation for power reduction in interconnects
Methods and apparatus relating to low-overhead utilization-aware link-width modulation to reduce power consumption in interconnects are described. In one...
US-9,336,156 Method and apparatus for cache line state update in sectored cache with line state tracker
A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request...
US-9,336,066 Hybrid linear validation algorithm for software transactional memory (STM) systems
A method and apparatus for hybrid validation for a Software Transaction Memory (STM) is herein described. During execution of a transaction, when acquiring...
US-9,336,040 Techniques for remapping sessions for a multi-threaded application
Examples may include a remapping of sessions for a multi-threaded application that may be executed at a server or a client coupled to the server via a plurality...
US-9,336,036 System method for memory virtualization control logic for translating virtual memory in space of guest memory...
A virtualization based system comprises a host and a plurality of virtual machines that may each comprises a guest memory. A virtual machine monitor has access...
US-9,336,008 Shared function multi-ported ROM apparatus and method
Various embodiments may be disclosed that may share a ROM pull down logic circuit among multiple ports of a processing core. The processing core may include an...
US-9,336,000 Instruction execution unit that broadcasts data values at different levels of granularity
An apparatus is described that includes an execution unit to execute a first instruction and a second instruction. The execution unit includes input register...
US-9,335,996 Recycling error bits in floating point units
A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably...
US-9,335,944 In-place change between transient and persistent state for data structures on non-volatile memory
Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one...
US-9,335,943 Method and apparatus for fine grain memory protection
An apparatus and method for fine grain memory protection. For example, one embodiment of a method comprises: performing a first lookup operation using a virtual...
US-9,335,933 Equalization for high speed input/output (I/O) link
Described are systems and apparatuses to mitigate the timing margin loss caused by inter-symbol interference (ISI) in high speed input/output (I/O) interfaces....
US-9,335,888 Full 3D interaction on mobile devices
Systems and methods may provide for displaying a three-dimensional (3D) environment on a screen of a mobile device, and identifying a user interaction with an...
US-9,335,814 Adaptively controlling low power mode operation for a cache memory
In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a cache memory including a plurality of portions...
US-9,335,813 Method and system for run-time reallocation of leakage current and dynamic power supply current
A method and system for dynamic or run-time reallocation of leakage current and dynamic power supply current of a processor. In one embodiment of the invention,...
US-9,335,808 Indicating critical battery status in mobile devices
An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The...
US-9,335,804 Distributing power to heterogeneous compute elements of a processor
In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute...
US-9,335,803 Calculating a dynamically changeable maximum operating voltage value for a processor based on a different...
In an embodiment, a processor includes voltage calculation logic to calculate a plurality of maximum operating voltage values each associated with a number of...
US-9,335,373 Memory channel having deskew separate from redrive
A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from...
US-9,332,643 Interconnect architecture with stacked flex cable
Stacked flex cable assemblies and their manufacture are described. One assembly includes a first flex cable and a second flex cable electrically coupled to the...
US-9,332,564 Method, apparatus and system to manage distributed channel access with time reservation
A method, apparatus and system to manage distributed channel access with time reservation are generally presented. In this regard, a reservation agent is...
US-9,332,551 Opportunistic resource sharing between devices
Techniques for opportunistic resource sharing between mobile devices are described. A method comprises identifying a set of homogeneous device resources...
US-9,332,469 Frequency offset measurement enhancements for long term evolution (LTE)
Embodiments for providing frequency offset measurement enhancements are generally described herein. In some embodiments, user equipment is informed of a...
US-9,332,456 Discontinuous reception (DRX) enhancements in LTE systems
Embodiments of a system and method for providing DRX enhancements in LTE systems are generally described herein. In some embodiments, a system control module is...
US-9,332,452 Radio communication devices and methods for controlling a radio communication device
A radio communication device may be provided. The radio communication device may include: a measurement circuit configured to measure a first reception quality...
US-9,332,451 Method and apparatus of requesting a beacon report
A beacon signal may be provided with data extensions. The data extensions permit additional information to be provided by the beacon signal, thereby reducing...
US-9,332,417 Apparatuses and methods for coordinating operations of multiple wireless communications modules with multiple...
A wireless communications device is provided with a plurality of card slots, a first wireless communications module, and a second wireless communications...
US-9,332,381 Location-based application recommendation
Described herein are techniques related to location-aware application recommendations in wireless devices. For example, an application recommendation alert may...
US-9,332,264 Configurable performance motion estimation for video encoding
A motion estimation engine may be implemented to include a skip checking module, an integer search module, a macroblock partitioning module, a fractional search...
US-9,331,935 Network device selection
An embodiment may include circuitry that may be capable of selecting, from network devices, at least one network device to which at least one packet is to be...
US-9,331,855 Apparatus, system, and method for providing attribute identity control associated with a processor
Described herein are an apparatus, system, and method for attribute identity control in a processor. The apparatus comprises a logic unit including a...
US-9,331,814 Hybrid automatic repeat-request combination for wireless transmissions
In one embodiment, a method for data communication may include receiving a first set of soft bit values in a Hybrid Automatic Repeat-Request (HARQ) buffer using...
US-9,331,795 Transmission arrangement and method for analyzing an amplified transmission signal
A transmission arrangement is disclosed having an amplifier which is set up to amplify a transmission signal and to provide it as an amplified transmission...
US-9,331,759 HARQ timing design for a TDD system
Disclosed are methods and apparatuses related to receiving one or more indications of time division duplex (TDD) uplink/downlink (UL/DL) configurations for two...
US-9,331,722 Feedback calibration of digital to time converter
This document discusses apparatus and methods for compensating non-linearity of digital-to-time converters (DTCs). In an example, a wireless device can include...
US-9,331,674 Multi-phase signal generator and multi-phase signal generating method thereof
A multi-phase signal generator and a multi-phase signal generating method thereof. The multi-phase signal generator includes a signal generator, a first...
US-9,331,017 Chip package incorporating interfacial adhesion through conductor sputtering
This disclosure relates generally to an electronic device and method having can include a method of making a chip package. An insulator layer comprising an...
US-9,330,999 Multi-component integrated heat spreader for multi-chip packages
A multi-component heat spreader comprising a top component having a first surface and an opposing second surface with either a cavity extending therein from the...
US-9,330,993 Methods of promoting adhesion between underfill and conductive bumps and structures formed thereby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include...
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