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Patent # Description
US-9,407,342 Protocol for MU MIMO operation in a wireless network
Various embodiments of the invention may modify the techniques used in conventional networks, to achieve techniques that are better suited for networks that use...
US-9,407,320 Detection of double talk in telecommunications networks
In one embodiment, the presence of double talk (DT) is detected in a telecommunications network having a near-end user and a far-end user. The energies of both...
US-9,407,302 Communication device, mobile terminal, method for requesting information and method for providing information
A communication device is described comprising a message generator configured to generate a message indicating that a mobile terminal is to determine whether a...
US-9,407,273 Digital delay-locked loop (DLL) training
A DLL may include a DLL training circuit that provides a feedback signal to the DLL and receives a first delay code value from the DLL that corresponds to the...
US-9,407,245 System for digitally controlled edge interpolator linearization
This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include...
US-9,407,229 Inverter- and-switched-capacitor-based squelch detector apparatus and method
A squelch detector includes is configured to receive a time-varying differential communication signal, and includes switched capacitors and an inverter...
US-9,407,227 Regulation of an amplification apparatus
An amplifier module comprises an amplifier having an output, a coupler coupled to the output to receive a first signal provided at the output and a power...
US-9,406,618 Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and...
An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a...
US-9,406,615 Techniques for forming interconnects in porous dielectric materials
Techniques are disclosed for forming interconnects in porous dielectric materials. In accordance with some embodiments, the porosity of a host dielectric layer...
US-9,406,587 Substrate conductor structure and method
Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods...
US-9,406,582 Apparatus to minimize thermal impedance using copper on die backside
A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen...
US-9,406,547 Techniques for trench isolation using flowable dielectric materials
Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a...
US-9,406,512 Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects
Self-aligned via patterning with multi-colored photobuckets for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for...
US-9,406,450 Energy storage devices with at least one porous polycrystalline substrate
In one embodiment, a structure for a energy storage device may include at one polycrystalline substrate. The grain size may be designed to be at least a size at...
US-9,406,427 Transformer devices
A planar transformer or balun device, having small trace spacing and high mutual coupling coefficient, and a method of fabricating the same is disclosed. The...
US-9,406,378 Phase change memory with mask receiver
Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the...
US-9,406,313 Adaptive microphone sampling rate techniques
An apparatus for adjusting a microphone sampling rate, the apparatus including an input to receive an audio signal from a microphone and a front-end processing...
US-9,406,295 Apparatus and method for voice based user enrollment with video assistance
Embodiments of apparatus and methods for voice based user enrollment with video assistance are described. In embodiments, an apparatus may include a face...
US-9,406,100 Image processing techniques for tile-based rasterization
Techniques are described that can delay or even prevent use of memory to store triangles associated with tiles as well as processing resources associated with...
US-9,405,937 Method and apparatus for securing a dynamic binary translation system
A processor and method are described for managing different privilege levels associated with different types of program code, including binary translation...
US-9,405,908 Systems, methods, and apparatus to virtualize TPM accesses
Embodiments of system, method, and apparatus for virtualizing TPM accesses is described. In some embodiments, an apparatus including a CPU core to execute a...
US-9,405,889 Device, method, and system for augmented reality security
Devices and methods for authenticating a user of a mobile computing device to a content server include establishing a communication session between a target...
US-9,405,782 Parallel operation in B+ trees
Embodiments of techniques and systems for parallel processing of B+ trees are described. A parallel B+ tree processing module with partitioning and ...
US-9,405,725 Writing message to controller memory space
An embodiment may include circuitry that may write a message from a system memory in a host to a memory space in an input/output (I/O) controller in the host. A...
US-9,405,724 Reconfigurable apparatus for hierarchical collective networks with bypass mode
A reconfigurable tree apparatus with a bypass mode and a method of using the reconfigurable tree apparatus are disclosed. The reconfigurable tree apparatus uses...
US-9,405,719 Circuitry to generate and/or use at least one transmission time in at least one descriptor
An embodiment may include circuitry that may generate and/or use, at least in part, at least one descriptor to be associated with at least one packet. The at...
US-9,405,718 Leveraging an enumeration and/or configuration mechanism of one interconnect protocol for a different...
An interconnect architecture device of an aspect includes a processor to generate a transaction that is of a different interconnect protocol than LLI. The...
US-9,405,707 Secure replay protected storage
Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such...
US-9,405,706 Instruction and logic for adaptive dataset priorities in processor caches
A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The...
US-9,405,701 Apparatus and method for accelerating operations in a processor which uses shared virtual memory
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an...
US-9,405,688 Method, apparatus, system for handling address conflicts in a distributed memory fabric architecture
Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and...
US-9,405,687 Method, apparatus and system for handling cache misses in a processor
In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion...
US-9,405,681 Workload adaptive address mapping
Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request...
US-9,405,647 Register error protection through binary translation
Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on...
US-9,405,600 Electronic device to provide notification of event
An electronic device may be provided that includes logic, at least partially implemented in hardware, to detect an occurrence of a blocking instance at the...
US-9,405,595 Synchronizing multiple threads efficiently
In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to...
US-9,405,570 Low latency virtual machine page table management
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views...
US-9,405,565 Virtualization event processing in a layered virtualization architecuture
Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an...
US-9,405,552 Method, device and system for controlling execution of an instruction sequence in a data stream accelerator
Techniques and mechanisms for controlling execution of an instruction sequence in a data stream processing engine. In an embodiment, a control unit of the data...
US-9,405,551 Creating an isolated execution environment in a co-designed processor
In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the...
US-9,405,547 Register allocation for rotation based alias protection register
A system may comprise an optimizer/scheduler to schedule on a set of instructions, compute a data dependence, a checking constraint and/or an anti-checking...
US-9,405,545 Method and apparatus for cutting senior store latency using store prefetching
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency...
US-9,405,539 Providing vector sub-byte decompression functionality
Methods, apparatus, instructions and logic provide SIMD vector sub-byte decompression functionality. Embodiments include shuffling a first and second byte into...
US-9,405,538 Functional unit having tree structure to support vector sorting algorithm and other algorithms
An apparatus is described having a functional unit of an instruction execution pipeline. The functional unit has a plurality of compare-and-exchange circuits...
US-9,405,537 Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm
An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a)...
US-9,405,477 Method and system for maintaining release consistency in shared memory programming
A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in...
US-9,405,358 Reducing power consumption of uncore circuitry of a processor
In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a...
US-9,405,351 Performing frequency coordination in a multiprocessor system
In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption...
US-9,405,345 Constraining processor operation based on power envelope information
In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a...
US-9,405,340 Apparatus and method to implement power management of a processor
In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating...
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