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| Patent # | Description |
|---|---|
| US-9,851,696 |
Circuit, a time-to-digital converter, an integrated circuit, a
transmitter, a receiver and a transceiver A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal... |
| US-9,851,561 |
Head-mounted device with rear-facing camera Various systems and methods for displaying a rearview camera feed in a head-mounted display are described herein. A system for displaying a rearview camera feed... |
| US-D806,087 |
Connector keyboard for an electronic device |
| US-9,848,510 |
Socket loading element and associated techniques and configurations Embodiments of the present disclosure are directed towards a socket loading element and associated techniques and configurations. In one embodiment, an... |
| US-9,846,410 |
Holographic display systems and methods having elliposidial arrangment of
DMD arrays emitting infrared laser... Systems, devices and methods are described including providing infrared (IR) laser radiation to a Digital Micromirror Device (DMD) array and using the DMD array... |
| US-9,844,144 |
Pogo pin integrated circuit package mount Apparatuses, systems and methods associated with electrical fast transient tolerant input/output (I/O) communication (e.g., universal serial bus (USB)) design... |
| US-9,844,068 |
Techniques for dynamic resource allocation Techniques are disclosed that dynamically allocate communications resources in a wireless communications network, such as a wireless personal area network... |
| US-9,844,054 |
Time division duplex (TDD) uplink downlink (UL-DL) reconfiguration An evolved node (eNB) operable to transmit a Time Division Duplex (TDD) uplink-downlink (UL-DL) reconfiguration in a heterogeneous network (HetNet) is... |
| US-9,844,049 |
Apparatus, method, and computer readable medium for initiating uplink
multi-user medium access in high... Apparatus, computer readable medium, and methods for initiating uplink multi-user medium access in high-efficiency wireless local-area networks (WLANs) are... |
| US-9,844,012 |
Automatic gain control gain adjustment A method of Automatic Gain Control (AGC) gain adjustment by a wireless device, including receiving a reference signal and data from a secondary cell operating... |
| US-9,843,959 |
Interference mitigation by a scalable digital wireless modem Described herein are technologies related to an implementation for dynamic adjustment of an out-of-band emission in a wireless modem, including spurious... |
| US-9,843,958 |
Communication of preferred power consumption configurations Technology for communicating power preference indication (PPI) message is described. A user equipment (UE) may receive PPI configuration information, from an... |
| US-9,843,956 |
Prioritized cell identification and measurement method A prioritized cell identification and measurement method is disclosed. The method classifies frequency layers to be monitored and measured by an user equipment... |
| US-9,843,850 |
Audio speakers with integrated sealing and assembly features for
"caseless" installation Small-scale audio speakers of various shapes are installed in parent devices. Inner casings, and the surrounding vibration-damping zone often required between... |
| US-9,843,768 |
Audience engagement feedback systems and techniques Embodiments of a system and method for indicating audience engagement are generally described herein. A method may include sending speech from a speaker to be... |
| US-9,843,474 |
Telemetry adaptation Methods, systems, and storage media for telemetry adaptation are disclosed herein. In an embodiment, a networking device may include a data collector agent... |
| US-9,843,441 |
Compact, low power advanced encryption standard circuit Embodiments of an invention for a compact, low power Advanced Encryption Standard circuit are disclosed. In one embodiment, an apparatus includes an encryption... |
| US-9,843,436 |
Flexible interconnect architecture A port is provided to facilitate a link between a first device and a second device. The port can include a driver circuit to support half duplex communication... |
| US-9,843,367 |
Enhanced node B and method for precoding with reduced quantization error Embodiments of an enhanced Node B (eNB) and method for precoding with reduced quantization error are generally described herein. In some embodiments, first and... |
| US-9,843,352 |
Method and apparatus for dynamic radio emission compliance monitoring The disclosure generally relates to a method, apparatus and system for identifying non-compliant radio emissions and for enforcing compliance. In one... |
| US-9,843,214 |
Wireless charging device for wearable electronic device Systems and methods may provide for wireless charging device of an electronic device powered by a rechargeable battery. The wireless charging device may include... |
| US-9,842,944 |
Solid-source diffused junction for fin-based electronics A solid source-diffused junction is described for fin-based electronics. In one example, a fin is formed on a substrate. A glass of a first dopant type is... |
| US-9,842,928 |
Tensile source drain III-V transistors for mobility improved n-MOS An n-MOS transistor device and method for forming such a device are disclosed. The n-MOS transistor device comprises a semiconductor substrate with one or more... |
| US-9,842,832 |
High density interconnection of microelectronic devices A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically... |
| US-9,842,818 |
Variable ball height on ball grid array packages by solder paste transfer BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold... |
| US-9,842,800 |
Forming interconnect structures utilizing subtractive paterning techniques Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate... |
| US-9,842,655 |
Reducing verification checks when programming a memory device Technology for an apparatus is described. The apparatus can include a memory controller with circuitry configured to initiate a program verify sequence to... |
| US-9,842,643 |
Apparatuses, methods, and systems for dense circuitry using tunnel field
effect transistors Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first... |
| US-9,842,624 |
Multiple camera video image stitching by placing seams for scene objects Image stitching is described for multiple camera video by placing seams for objects in the scene. An object of interest is identified within an overlap between... |
| US-9,842,241 |
Biometric cryptography using micromachined ultrasound transducers An embodiment includes an ultrasonic sensor system comprising: a backend material stack including a first metal layer between a substrate and a second metal... |
| US-9,842,213 |
Mechanisms for locking computing devices Various systems and methods for locking computing devices are described herein. In an example, a portable device comprises an electro-mechanical lock; and a... |
| US-9,842,156 |
System and method for providing differentiated storage service in a
database In accordance with some embodiments, classification of input/output requests from a database to a storage system may be performed. Each input/output request may... |
| US-9,842,082 |
Dynamically updating logical identifiers of cores of a processor In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to... |
| US-9,842,065 |
Virtualization-based platform protection technology A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The... |
| US-9,842,056 |
Systems and methods for non-blocking implementation of cache flush
instructions Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a... |
| US-9,842,046 |
Processing memory access instructions that have duplicate memory indices A method of an aspect includes receiving an instruction indicating a first source packed memory indices, a second source packed data operation mask, and a... |
| US-9,842,022 |
Technologies for reducing latency in read operations Technologies for reducing latency in read operations include an apparatus to perform a read attempt of a target data set from a memory, to obtain a candidate... |
| US-9,842,021 |
Memory device check bit read mode A check bit read mode enables a memory device to provide internal check bits to an associated host. A memory controller of a memory subsystem can generate one... |
| US-9,842,015 |
Instruction and logic for machine checking communication A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is... |
| US-9,842,005 |
Register file segments for supporting code block execution by using
virtual cores instantiated by partitionable... A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving... |
| US-9,841,997 |
Method and apparatus for execution mode selection An apparatus and method for performing high performance instruction emulation. One embodiment of the invention includes a processor to process an instruction... |
| US-9,841,920 |
Heterogeneous memory die stacking for energy efficient computing Methods and apparatus to provide heterogeneous memory die stacking for energy efficient computing are described. In one embodiment, a Phase Change Memory with... |
| US-9,841,807 |
Method and apparatus for a zero voltage processor sleep state Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A... |
| US-9,841,803 |
Independent power control of processing cores Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least... |
| US-9,841,784 |
Apparatus and method for controlling wearable devices using wireless
energy harvesting Described is an apparatus which comprises: an antenna to sense or receive energy from an external source; a harvesting module to harvest power according to the... |
| US-9,841,783 |
System to account for irregular display surface physics This disclosure is directed to a system to account for irregular display surface physics. In one embodiment, an example device may comprise a display including... |
| US-9,841,491 |
Enhanced positioning system using hybrid filter The disclosure generally relates to an enhanced positioning system and method using a combination or hybrid filter. In one embodiment, Time-Of-Flight (ToF)... |
| US-D805,068 |
Computing device |
| US-D805,046 |
Wireless electronic video device |
| US-9,839,134 |
Flexible integrated circuit that includes an antenna A flexible integrated circuit that includes a first dielectric layer having a first section at one polarity and a second section at an opposing polarity,... |
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