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Patent # Description
US-9,363,203 Modular interconnect structure
Some embodiments of the invention include an interconnect structure to transfer data among a plurality of devices. The interconnect structure includes a...
US-9,363,136 Mechanism to monitor quality of service
A processing device includes a processor to generate a plurality of events, an interface circuit coupled to the processor comprising one or more multiplexers to...
US-9,363,117 Method, baseband signal generator and computer program for providing a baseband signal
A method (100) for providing a baseband signal comprises monitoring (102) a disparity between a first magnitude of a first signal component (202) and a second...
US-9,363,070 Low power squelch circuit
Described herein is a low power squelch circuit which comprises a clock generation unit to generate first and second phases of a clock signal; a sampling unit...
US-9,363,068 Vector processor having instruction set with sliding window non-linear convolutional function
A processor is provided having an instruction set with a sliding window non-linear convolution function. A processor obtains a software instruction that...
US-9,362,998 Hybrid automatic repeat request-acknowledge (HARQ-ACK) codebook generation for inter-band time division duplex...
Technology to determine a Hybrid Automatic Repeat reQuest-ACKnowledge (HARQ-ACK) codebook size for inter-band time division duplex (TDD) carrier aggregation...
US-9,362,991 Apparatus, system and method of transmit power control for wireless communication
Some demonstrative embodiments include apparatuses, systems and/or methods of transmit power control for wireless communication. For example, an apparatus may...
US-9,362,977 Incremental preamble detection
In one embodiment, the present invention is a method for performing incremental preamble detection in a wireless communication network. The method processes...
US-9,362,813 Controller and a method for controlling a process variable and a power supply circuit comprising a power supply...
A controller (100; 200) for controlling a process variable (202) comprises an input interface (102) configured to receive a feedback signal indicative of an...
US-9,362,684 Rate scalable connector for high bandwidth consumer applications
Methods and systems may include an input/output (IO) interface that has an integrated buffer, a housing and a substrate disposed within the housing. The...
US-9,362,369 Group III-N transistors on nanoscale template structures
A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall....
US-9,362,253 Bumpless build-up layer package with pre-stacked microelectronic devices
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL)...
US-9,362,233 Radio frequency shielding within a semiconductor package
Radio frequency shielding within a semiconductor package is described. In one example, a multiple chip package has a digital chip, a radio frequency chip, and...
US-9,362,232 Apparatus and method for embedding components in small-form-factor, system-on-packages
According to various aspects of the present disclosure, an apparatus is disclosed that includes a small form factor mobile platform including a ...
US-9,362,144 Article and panel comprising semiconductor chips, casting mold and methods of producing the same
A panel with a reconfigured wafer including semiconductor chips arranged in rows and columns on semiconductor device positions includes: at least one...
US-9,362,074 Nanowire-based mechanical switching device
Nanowire-based mechanical switching devices are described. For example, a nanowire relay includes a nanowire disposed in a void disposed above a substrate. The...
US-9,361,972 Charge level maintenance in a memory
In one embodiment, a memory such as a dynamic random access memory employs charge boosting to bitcells prior to sensing charge levels in the storage nodes of...
US-9,361,970 Configuration for power reduction in DRAM
Disclosed embodiments may include an apparatus having a segment wordline enable coupled to logic to selectively disable ones of a number of segment wordline...
US-9,361,833 Eye tracking based selectively backlighting a display
Systems, apparatus, articles, and methods are described including operations for eye tracking based selective backlighting of a display.
US-9,361,718 Interactive screen viewing
The presentation of a computer display may be modified based on what the user is viewing on the display. In one embodiment, gaze detection technology may be...
US-9,361,537 Techniques to reduce color artifacts in a digital image
Techniques for reducing color artifacts in a digital image are described. In one embodiment, for example, an apparatus may comprise logic, at least a portion of...
US-9,361,519 Computational array camera with dynamic illumination for eye tracking
Methods and systems for eye tracking are disclosed. One such method obtains a plurality of images of the eye from an array camera and detects glint positions...
US-9,361,510 Efficient facial landmark tracking using online shape regression method
Disclosed in some examples are various modifications to the shape regression technique for use in real-time applications, and methods, systems, and machine...
US-9,361,498 Optical communication using differential images
Techniques related to optical communication including techniques for communicating barcodes using differential images.
US-9,361,471 Secure vault service for software components within an execution environment
Embodiments of apparatuses, articles, methods, and systems for secure vault service for software components within an execution environment are generally...
US-9,361,465 Privacy-enhanced car data distribution
In accordance with some embodiments, data may be collected from vehicles, and then reported to various subscribers with different levels of access privileges...
US-9,361,257 Mechanism for facilitating customization of multipurpose interconnect agents at computing devices
A mechanism is described for facilitating customization of multipurpose interconnect agents at computing devices according to one embodiment of the invention. A...
US-9,361,244 Apparatus for hardware accelerated runtime integrity measurement
Techniques are described for providing processor-based dedicated fixed function hardware to perform runtime integrity measurements for detecting attacks on...
US-9,361,234 Utilization of processor capacity at low operating frequencies
In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a...
US-9,361,233 Method and apparatus for shared line unified cache
An apparatus and method for implementing a shared unified cache. For example, one embodiment of a processor comprises: a plurality of processor cores grouped...
US-9,361,217 Methods and apparatus to manage workload memory allocation
Methods, articles of manufacture, and apparatus are disclosed to manage workload memory allocation. An example method includes identifying a primary memory and...
US-9,361,152 Transactional memory management techniques
Techniques for improved transactional memory management are described. In one embodiment, for example, an apparatus may comprise a processor element, an...
US-9,361,121 System and method for execution of a secured environment initialization instruction
A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates...
US-9,361,116 Apparatus and method for low-latency invocation of accelerators
An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises: a...
US-9,361,106 SMS4 acceleration processors, methods, systems, and instructions
A processor of an aspect includes a plurality of packed data registers and a decode unit to decode an instruction. The instruction is to indicate one or more...
US-9,361,101 Extension of CPU context-state management for micro-architecture state
A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. A save instruction is executed to store a...
US-9,361,100 Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements
A processor includes a first register with first, second, third, and fourth data elements. A second register to hold fifth, sixth, seventh, and eighth data...
US-9,361,064 Methods and systems to compensate for non-linearity of a stochastic system
Determination of digital compensation to compensate for non-linearity of stochastic system configured to sample a phase difference, based on statistical...
US-9,361,059 Architecture for seamless integrated display system
Embodiments of systems and methods of seamless displays are generally described herein. In some embodiments, a backpanel device comprising display drive...
US-9,360,933 Virtual links between different displays to present a single virtual object
Virtual links are used between two different displays to represent a single virtual object. In one example, the invention includes generating a...
US-9,360,927 Power efficient processor architecture
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core...
US-9,360,924 Reduced power mode of a cache unit
In an embodiment, a processor includes a plurality of cores and a cache unit reserved for a first core of the plurality of cores. The cache unit may include a...
US-9,360,920 Reducing power consumption in a fused multiply-add (FMA) unit of a processor
In one embodiment, the present invention includes a processor having a fused multiply-add (FMA) unit to perform FMA instructions and add-like instructions. This...
US-9,360,909 System, method and apparatus for energy efficiency and energy conservation by configuring power management...
According to one embodiment of the invention, an integrated circuit device at least one compute engine and a control unit. Coupled to the compute engine(s), the...
US-9,360,896 Low-profile hinge for an electronic device
Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a...
US-9,360,889 Routing signals via hinge assemblies for mobile computing devices
Embodiments of the invention describe a hinge assembly to rotatably couple a first housing to a second housing, wherein an interconnect extends through the...
US-9,360,601 On-chip diffraction grating prepared by crystallographic wet-etch
Methods of forming microelectronic structures are described. Embodiments of those methods may include forming a photomask on a (110) silicon wafer substrate,...
US-9,360,503 Method for determining a sampling time of a signal, device for determining the same, and method for determining...
A method for determining a sampling time of a signal, the method including: determining a candidate sampling time of a signal for input to a sampling circuit;...
US-9,360,502 Increasing current carrying capability through direct liquid cooling of test contacts
Testing methods and systems are described. One method for testing an electronic device includes providing a probe in electrical contact with a device. The...
US-9,357,582 Simultaneous secondary-cell release for licensed shared access
A 3GPP LTE protocol enhancement realizes the full benefit of dynamic frequency sharing systems by enhancing current Secondary-Cell (SCell) release mechanisms to...
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