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Patent # Description
US-9,424,034 Multiple register memory access instructions, processors, methods, and systems
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction...
US-9,424,031 Techniques for enabling bit-parallel wide string matching with a SIMD register
Various embodiments are generally directed to overcoming limitations of vector registers in their use with bit-parallel string matching algorithms. An apparatus...
US-9,423,959 Method and apparatus for store durability and ordering in a persistent memory architecture
An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises:...
US-9,423,901 System and method to control screen capture
Various systems and methods for controlling screen captures are described herein. A system comprises a touchscreen; a display module communicatively coupled to...
US-9,423,895 Dual touch surface multiple function input device
For one disclosed embodiment, an apparatus includes a first housing and a second housing coupled to the first housing. The first housing and the second housing...
US-9,423,858 Sharing power between domains in a processor package using encoded power consumption information from a second...
In an embodiment, the present invention includes a processor having a first domain with at least one core to execute instructions, a second domain coupled to...
US-9,423,828 Self-leveling system with auto feedback control
A leveling system includes a chassis and a first foot protruding from the chassis. The leveling system also includes a plurality of pressure sensors to measure...
US-D764,563 Projector
US-9,420,707 Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers...
US-9,420,700 Inclined photonic chip package for integrated optical transceivers and optical touchscreen assemblies
An optical touchscreen assembly may employ a photonic chip packaged with a chip surface at an angle inclined between horizontal and vertical orientations. An...
US-9,420,693 Integration of embedded thin film capacitors in package substrates
An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a...
US-9,420,634 User equipment having virtual mobile terminals
Embodiments of the present disclosure describe methods, apparatuses, and systems related to a user equipment having virtual mobile terminals. Other embodiments...
US-9,420,627 Systems, methods, and devices with different radio link failure timers based on user equipment speed
Systems, methods, and device for adjusting an operation time of a radio link failure timer are disclosed herein. User equipment (UE) may be configured to...
US-9,420,537 Queueing mechanism for client-side network traffic to reduce radio power consumption on mobile clients
Embodiments described herein relate generally to delaying the transmission of a plurality of data packets. A device may enter a packet-delay mode based on an...
US-9,420,532 Shaping data packet traffic
According to some embodiments, a communication module 120 may be configured to transmit data packet traffic and a management module 110 may be configured to...
US-9,420,511 Signaling QoS requirements and UE power preference in LTE-A networks
Embodiments for signaling quality of service (QoS) requirements and user equipment (UE) power preference in LTE-A networks are generally described herein. In...
US-9,420,475 Radio communication devices and methods for controlling a radio communication device
A radio communication device may be provided. The radio communication device may include: a receiver configured to receive data; a buffer configured to buffer a...
US-9,420,464 Technologies for controlling network access based on electronic device communication fingerprints
Technologies for monitoring network access and/or usage include mobile computing devices in communication with network devices to facilitate access to a...
US-9,420,429 Techniques for trusted location application and location provider communications
Various embodiments are generally directed to techniques for conveying location information between a location provider and a trusted location application...
US-9,419,976 Method and apparatus to using storage devices to implement digital rights management protection
Embodiments of systems, apparatuses, and methods to securely download digital rights managed content with a client are described. In some embodiments, a system...
US-9,419,973 Content URL authentication for dash
Technology for content uniform resource locator (URL) authentication for dynamic adaptive streaming over hypertext transfer protocol (HTTP) (DASH) is disclosed....
US-9,419,972 Two dimensional direct memory access scheme for enhanced network protocol processing performance
Systems and methods are directed to a memory device that includes a plurality of memory buffers and a direct memory access (DMA) descriptor structure. The DMA...
US-9,419,830 Device, system and method of communicating a wireless communication orthogonal-frequency-division-multiplexing...
Some demonstrative embodiments include devices, systems and/or methods of communicating a wireless orthogonal-frequency-division-multiplexing (OFDM) signal. For...
US-9,419,829 Apparatus, system and method of direct current (DC) estimation of a wireless communication packet
Some demonstrative embodiments include devices, systems and/or methods of Direct Current (DC) estimation. For example, an apparatus may include an estimator to...
US-9,419,802 Secure message filtering to vehicle electronic control units with secure provisioning of message filtering rules
A method according to one embodiment includes the operations of configuring a host processor to receive a message filtering rule, the host processor associated...
US-9,419,792 Instruction for accelerating SNOW 3G wireless security algorithm
Vector instructions for performing SNOW 3G wireless security operations are received and executed by the execution circuitry of a processor. The execution...
US-9,419,732 Systems and methods for optimized decoding of in-band on-channel (IBOC) services
Certain embodiments herein are directed to optimized decoding of in-band on-channel (IBOC) services, such as audio, traffic, and data associated with HD...
US-9,419,694 Beamforming using base and differential codebooks
Embodiments of methods and apparatus for determining and/or quantizing a beamforming matrix are disclosed. In some embodiments, the determining and/or...
US-9,419,677 Removal of modulated tonal interference
In some embodiments a phase between a periodic spreading signal and an effective spreading signal modulating an interfering harmonic is determined, an amplitude...
US-9,419,657 Hybrid I/Q and polar transmitter
A hybrid polar I-Q transmitter includes an I-Q derivation circuit configured to receive a first and second I-Q data components comprising a first I-Q data pair,...
US-9,419,656 Decoder and method for decoding an encoded sequence of bits
A decoder including an input, a branch metric unit, a path metric unit, a starting state unit, and a tail path forcing unit, or alternatively, a state...
US-9,419,648 Supporting data compression using match scoring
In one embodiment, a processing system is provided. The processing system includes a memory for storing an input bit stream and a processing logic coupled to...
US-9,419,647 Partitioned data compression using accelerator
In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to: receive...
US-9,419,339 Package structures including discrete antennas assembled on a device
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include...
US-9,419,212 Barrier film techniques and configurations for phase-change memory elements
Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus...
US-9,419,140 Two-dimensional condensation for uniaxially strained semiconductor fins
Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based...
US-9,419,106 Non-planar transistors and methods of fabrication thereof
The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar...
US-9,418,997 Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
US-9,418,912 Methods of forming serpentine thermal interface material and structures formed thereby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal...
US-9,418,906 Space and cost efficient incorporation of specialized input-output pins on integrated circuit substrates
In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at...
US-9,418,898 Integrated circuits with selective gate electrode recess
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling...
US-9,418,888 Non-lithographically patterned directed self assembly alignment promotion layers
A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a...
US-9,418,783 Inductor design with metal dummy features
Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design...
US-9,418,761 Apparatus for boosting source-line voltage to reduce leakage in resistive memories
Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a...
US-9,418,759 Assist circuits for SRAM testing
Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist...
US-9,418,752 Ramping inhibit voltage during memory programming
The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit...
US-9,418,723 Techniques to reduce memory cell refreshes for a memory device
Examples may include techniques to reduce memory cell refreshes for a memory device. These techniques include a control unit receiving a command to cause an...
US-9,418,700 Bad block management mechanism
A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and...
US-9,418,625 Resolution loss mitigation for 3D displays
Systems, devices and methods are described including determining a display type and a display mode, preparing stereoscopic image content in response to the...
US-9,418,529 Methods and arrangements for sensors
Generally, smart sensors, logic to process messages from smart sensors, and smart sensor systems are described herein. Embodiments may comprise logic such as...
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