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Patent # Description
US-9,373,182 Memory sharing via a unified memory architecture
A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein....
US-9,372,993 Methods and apparatus to protect memory regions during low-power states
A disclosed example method involves configuring a processor to, when transitioning the processor system to a low-power mode, use a key and a random or...
US-9,372,988 User controllable platform-level trigger to set policy for protecting platform from malware
Embodiments of systems, apparatuses, and methods to protect data stored in a storage system of a device from malware alternation are described. In some...
US-9,372,984 Authenticated launch of virtual machines and nested virtual machine managers
An embodiment of the invention provides for an authenticated launch of VMs and nested VMMs. The embodiment may do so using an interface that invokes a VMM...
US-9,372,980 Orientation aware authentication on mobile platforms
Systems and methods may provide for receiving an authentication input and determining an authentication orientation of a mobile platform during entry of the...
US-9,372,816 Advanced programmable interrupt controller identifier (APIC ID) assignment for a multi-core processing unit
Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign each active and eligible core a unique...
US-9,372,812 Determining policy actions for the handling of data read/write extended page table violations
Embodiments of systems, apparatuses, and methods for determining if an instruction of a virtual machine is allowed to modify a protected memory region are...
US-9,372,807 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-9,372,806 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-9,372,768 Debug interface
Techniques of debugging a computing system are described herein. The techniques may include generating debug data at agents in the computing system. The...
US-9,372,764 Event counter checkpointing and restoring
Event counter checkpointing and restoring is disclosed. In one implementation, a processor includes a first event counter to count events that occur during...
US-9,372,752 Assisted coherent shared memory
An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes....
US-9,372,698 Method and apparatus for implementing dynamic portbinding within a reservation station
A processor and method are described for scheduling operations for execution within a reservation station. For example, a method in accordance with one...
US-9,372,692 Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality...
US-9,372,678 Compiler optimization for complex exponential calculations
Technologies for optimizing complex exponential calculations include a computing device with optimizing compiler. The compiler parses source code, optimizes the...
US-9,372,677 Register liveness analysis for SIMD architectures
Systems and methods of allocating physical registers to variables may involve identifying a partial definition of a variable in an inter-procedural control flow...
US-9,372,663 Direct digital synthesis of signals using maximum likelihood bit-stream encoding
Methods and apparatus are provided for direct synthesis of RF signals using maximum likelihood sequence estimation. An RF digital RF input signal is synthesized...
US-9,372,526 Managing a power state of a processor
A method and system for managing a power state of a processor are described herein. The method includes receiving, at the processor, a signal indicating that an...
US-9,372,524 Dynamically modifying a power/performance tradeoff based on processor utilization
In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy...
US-9,372,507 Adjustable support and a mobile computing device having an adjustable support
A support that is selectively adjustable to a plurality of configurations that enable a variety of viewing/user orientations of a mobile device. The mobile...
US-9,372,501 Block aligner-based dead cycle deskew method and apparatus
A method and apparatus to deskew dead cycles is described using a block aligner. In one example a method includes receiving a sequence of bytes into a first...
US-9,371,676 360 degree hinge assembly for electronic devices
In one example a hinge assembly for an electronic device comprises a linkage comprising a first bushing disposed at a first end of the linkage and a second...
US-9,370,018 Techniques for uplink power control
Examples are disclosed for determining, at a base station, separate open loop power control factors for one or more uplink interference patterns based on...
US-9,370,011 Techniques to provide physical resource allocation using a tree-based structure and communicate a channel...
In a wireless network, simultaneous support of distributed and contiguous sub-carrier allocation may be accomplished in the same sub-frame or time zone....
US-9,369,982 Online adaptive fusion framework for mobile device indoor localization
This disclosure describes systems, methods, and computer-readable media related to employing particle filter methods to estimate the location of a mobile...
US-9,369,977 Methods and arrangements for synch frame transmissions
Logic to manage synch frame transmissions in a synch network via helper stations (STAs) synched to the network. Logic may coordinate actions of helper STAs via...
US-9,369,948 Method and related mobile device for cell search in multi radio access technology systems
In one implementation, a radio is tuned to a frequency and bandwidth such that it can accommodate a plurality of frequency channels of a plurality of RATs....
US-9,369,922 Periodic channel state information reporting for coordinated multipoint (CoMP) systems
Technology for periodic channel state information (CSI) reporting from a user equipment (UE) configured for carrier aggregation is disclosed. One method can...
US-9,369,912 Communication path switching for mobile devices
Methods, systems, and devices for switching internet protocol (IP) flows from a first communication path to a second communication path are disclosed herein. A...
US-9,369,911 Method and apparatus for enhanced uplink multiplexing
A method and apparatus for multiplexing are disclosed. Data is received over a plurality of logical channels. Data from the plurality of logical channels is...
US-9,369,867 Mobile platform software update with secure authentication
Generally, this disclosure describes devices, methods and systems and for securely updating software on a mobile platform using trusted hardware based...
US-9,369,856 Service of an emergency event based on proximity
An apparatus and system for communicating information relating to an emergency event occurring at a non-emergency vehicle to an emergency service includes...
US-9,369,822 Reporting power disruptions of machine-to-machine devices
Embodiments of the present disclosure describe device, methods, computer-readable media and system configurations for communication of notifications of...
US-9,369,774 System and method for controlling home network devices using multicast enabled remote controls
A system, method, and article of manufacture for controlling home network devices using a multicast enabled remote control. The system includes a plurality of...
US-9,369,735 Method and apparatus for adaptively reducing artifacts in block-coded video
Apparatus, systems and methods for adaptively reducing blocking artifacts in block-coded video are disclosed. In one implementation, a system includes...
US-9,369,727 Storage of depth information in a digital image file
Techniques are disclosed for encoding depth-enabled digital images in a file format, such as JPEG. In addition to compressed image data, calibration, disparity...
US-9,369,661 Real-time interactive personal video recorder interface
Interacting with a television program includes beginning playback of the program for perception by a user, analyzing the program to detect a cue within the...
US-9,369,551 Apparatus, system and method of protocol adaptation layer (PAL) communication to indicate transitioning a...
Some demonstrative embodiments include apparatuses, systems and/or methods of transitioning a device to a default state. For example, an apparatus may include a...
US-9,369,522 Scalable network apparatus for content based switching or validation acceleration
A network apparatus is provided that may include one or more security accelerators. The network apparatus also includes a plurality of network units cascaded...
US-9,369,441 End-to-end secure communication system
The present disclosure is directed to an end-to-end secure communication system wherein, in addition to encrypting transmissions between clients, ...
US-9,369,277 Encryption code generation using spin-torque NANO-oscillators
Embodiments include apparatuses, methods, and systems for generation of an encryption key. In various embodiments, an authentication circuit may include a first...
US-9,369,235 Maximizing data rate by adjusting codes and code rates
The present invention provides for making code rate adjustments and modulation type adjustments in a pseudonoise (PN) encoded CDMA system. Coding rate...
US-9,369,225 Distribution of an electronic reference clock signal that includes delay and validity information
An integrated circuit has a clock subsystem, and a circuit. The clock subsystem is configured to provide a reference clock signal to a first module and a second...
US-9,369,217 Cellular up-link harmonic spurs mitigation in Wi-Fi and bluetooth receivers
An interfering signal from a co-running modem is filtered using a notch filter to cancel high frequency harmonic interference to a received radio frequency (RF)...
US-9,369,188 Link prediction based re-beamforming triggering algorithm for 60 ghz communication links
A system and method are provided to trigger re-beamforming based on an algorithm that assesses various link characteristics. The algorithm is based on the...
US-9,369,136 Digital phase controlled delay circuit
An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from...
US-9,368,956 Electrostatic discharge clamp compatible with a fast ramping supply
Described herein is an apparatus and system of an electrostatic discharge circuit. The apparatus comprises: a clamp transistor with a terminal coupled to a node...
US-9,368,861 Omni directional broadband coplanar antenna element
The present invention provides an omni-directional antenna element configuration having a compensated radiation pattern. Broadband antenna elements are...
US-9,368,583 Field effect transistor with narrow bandgap source and drain regions and method of fabrication
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer...
US-9,368,461 Contact pads for integrated circuit packages
Disclosed herein are contact pads for use with integrated circuit (IC) packages. In some embodiments, a contact pad disclosed herein may be disposed on a...
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