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Patent # Description
US-9,397,689 Interpolator systems and methods
A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a...
US-9,397,683 Reduced digital audio sampling rates in digital audio processing chain
Reduced digital audio sampling rates are described in a digital audio processing chain. In one embodiment, an audio signal is received. A convolution operation...
US-9,397,641 Apparatus and method for low power fully-interruptible latches and master-slave flip-flops
Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first...
US-9,397,566 Master-slave digital voltage regulators
Described is an apparatus which comprises: a first bridge to be coupled to a first load; a first Pulse Width Modulation (PWM) circuit to drive the first bridge;...
US-9,397,506 Voltage management device for a stacked battery
An apparatus is provided that includes a first terminal to couple to a first node of a stacked battery pack having a first cell block and a second cell block, a...
US-9,397,471 Heat removal from photonic devices
Embodiments of the present description relate to mechanisms for transferring heat through a microelectronic substrate from a photonic device to a heat...
US-9,397,188 Group III-N nanowire transistors
A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a...
US-9,397,166 Strained channel region transistors employing source and drain stressors and systems including the same
Embodiments of the present invention provide transistor structures having strained channel regions. Strain is created through lattice mismatches in the source...
US-9,397,165 Active regions with compatible dielectric layers
A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure...
US-9,397,143 Liner for phase change memory (PCM) array and associated techniques and configurations
Embodiments of the present disclosure describe a liner for a phase change memory (PCM) array and associated techniques and configurations. In an embodiment, a...
US-9,397,102 III-V layers for N-type and P-type MOS source-drain contacts
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example...
US-9,397,079 Multichip integration with through silicon via (TSV) die embedded in package
Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as...
US-9,397,071 High density interconnection of microelectronic devices
A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically...
US-9,397,019 Integrated circuit package configurations to reduce stiffness
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed...
US-9,397,016 Flip chip assembly process for ultra thin substrate and package on package assembly
In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless...
US-9,396,883 Faradaic energy storage device structures and associated techniques and configurations
Embodiments of the present disclosure are directed towards Faradaic energy storage device structures and associated techniques and configurations. In one...
US-9,396,787 Memory operations using system thermal sensor data
Memory operations using system thermal sensor data. An embodiment of a memory device includes a memory stack including one or more coupled memory elements, and...
US-9,396,785 Memory device refresh commands on the fly
On the fly switching from one memory device refresh rate to another is provided. Control logic associated with the memory device detects a condition to switch...
US-9,396,784 Reduction of power consumption in memory devices during refresh modes
Devices, systems, and methods include an active mode to accommodate read/write operations of a memory device and a self-refresh mode to accommodate recharging...
US-9,396,582 Five-dimensional rasterization with conservative bounds
A per-tile test in the 5D rasterizer outputs intervals for both lens parameters, (u,v), and for time, t, as well as for depth z. These intervals are...
US-9,396,519 Content aware video resizing
Content aware video resizing is described. In one example, edge detection is done on pixel values of video frames. The edges are compared and an energy is...
US-9,396,513 Using group page fault descriptors to handle context switches and process terminations in graphics processors
Methods and systems may provide for detecting an end of execution of a process on a graphics processor and providing a group page fault descriptor to a page...
US-9,396,408 Techniques for improving stereo block matching with the pyramid method
Techniques to determine a search range for a stereo based matching pyramid. A first disparity estimation value for a first level in a stereo based matching...
US-9,396,384 User authentication via image manipulation
Various systems and methods for authenticating users via image manipulation are described herein. An initial image associated with a stored profile of a user...
US-9,396,329 Methods and apparatus for a safe and secure software update solution against attacks from malicious or...
Described herein are articles, systems, and methods for using a storage controller to protect secure data blocks through the enforcement of a read only policy....
US-9,396,152 Device, system and method for communication with heterogenous physical layers
A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device...
US-9,396,151 PCI express tunneling over a multi-protocol I/O interconnect
Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for...
US-9,396,120 Adjustable over-restrictive cache locking limit for improved overall performance
Disclosed is a cache locking system that includes a cache controller that is operable to receive a first request from a device to lock a first way in the cache....
US-9,396,118 Efficient dynamic randomizing address remapping for PCM caching to improve endurance and anti-attack
A method, including monitoring, by a remapping manager, a system state of a computing device for the occurrence of a predefined event, detecting, by the...
US-9,396,065 Extensible memory hub
The present disclosure relates to an extensible memory hub. An apparatus may include a first extensible non-volatile memory (NVM) hub (EN hub). The first EN hub...
US-9,396,059 Exchange error information from platform firmware to operating system
A computing system can include a platform firmware to monitor hardware errors and to notify an operating system when a corrective action is to be performed to...
US-9,396,056 Conditional memory fault assist suppression
In some disclosed embodiments instruction execution logic provides conditional memory fault assist suppression. Some embodiments of processors comprise a decode...
US-9,396,032 Priority based context preemption
Methods and apparatuses may prioritize the processing of high priority and low priority contexts submitted to a processing unit through separate high priority...
US-9,396,020 Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled...
An apparatus is described having multiple cores, each core having: a) an accelerator; and, b) a general purpose CPU coupled to the accelerator. The general...
US-9,396,000 Methods and systems to permit multiple virtual machines to separately configure and access a physical device
Methods and systems to permit multiple virtual machines (VMs) to separately configure and access a physical resource, substantially outside of a virtual machine...
US-9,395,994 Embedded branch prediction unit
In accordance with some embodiments of the present invention, a branch prediction unit for an embedded controller may be placed in association with the...
US-9,395,993 Execution-aware memory protection
Execution-Aware Memory protection technologies are described. A processor includes an instruction fetch unit to fetch instructions of applications executing in...
US-9,395,990 Mode dependent partial width load to wider register processors, methods, and systems
A method of an aspect is performed by a processor. The method includes receiving a partial width load instruction. The partial width load instruction indicates...
US-9,395,980 Residual addition for video software techniques
According to some embodiments, a technique provides for the execution of an instruction that includes receiving residual data of a first image and decoded...
US-9,395,903 Sharing information between computing devices
Technologies for sharing information between computing devices comprises determining a location of a recipient destination computing device relative to a source...
US-9,395,821 Systems and techniques for user interface control
Embodiments of systems and techniques for user interface (UI) control are disclosed herein. In some embodiments, a UI control system may determine locations of...
US-9,395,820 Techniques for notebook hinge sensors
Techniques are described for notebook hinge sensors. For example, a computing device may comprise a housing having a processor circuit and an input device, the...
US-9,395,806 Method and apparatus for a power-efficient framework to maintain data synchronization of a mobile personal...
An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment,...
US-9,395,796 Dynamic graphics geometry preprocessing frequency scaling and prediction of performance gain
Technologies are presented that optimize graphics processing performance. A method of frequency scaling may include beginning a graphics workload with a...
US-9,395,788 Power state transition analysis
Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by...
US-9,395,784 Independently controlling frequency of plurality of power domains in a processor system
In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core...
US-9,395,774 Total platform power control
Methods and apparatus relating to total platform power control are described. In one embodiment, power consumption by one or more processor cores of a processor...
US-9,395,762 Hinge configuration for an electronic device
Particular embodiments described herein provide for an electronic device, such as a notebook computer or laptop, that includes a circuit board coupled to a...
US-9,395,698 Bang-bang time to digital converter systems and methods
A time to digital converter includes a mutual exclusion element and a sampling component. The mutual exclusion element is configured to receive a first clock...
US-9,395,613 Optical device
According to the present invention, there is provided an optical device comprising, a plurality of light sources each operable to provide a light beam; at least...
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