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Patent # Description
US-1,018,7385 Techniques for extending communications chain of trust to client applications
Various embodiments are generally directed to techniques to form secure communications between two computing devices in which the chain of trust of those...
US-1,018,7308 Virtual switch acceleration using resource director technology
A virtual switch configured to switch packets between virtual switch ports based on classifier sub-tables. The virtual switch reserves blocks of last level...
US-1,018,7238 Wireless device, method, and computer readable media for signaling a short training field in a high-efficiency...
Apparatuses, methods, and computer readable media for signaling high efficiency short training field are disclosed. A high-efficiency wireless local-area...
US-1,018,7235 Long range bluetooth low energy synchronization system
A synchronizer can include a symbol estimator, an inner-pattern de-mapper, a timing tracker, and a correlator. The symbol estimator can be configured to...
US-1,018,7208 RSA algorithm acceleration processors, methods, systems, and instructions
A processor includes a decode unit to decode an instruction. The instruction indicates a first 64-bit source operand having a first 64-bit value, indicates a...
US-1,018,7132 Communication terminal and method for selecting a transmission antenna
According to an example, a communication terminal is described including a plurality of antennas, a transceiver configured to receive a message indicating a...
US-1,018,7064 Systems and methods for routing data across regions of an integrated circuit
An integrated circuit may include multiple programmable logic regions and a first plurality of routers. Each of the first plurality of routers is coupled to a...
US-1,018,6891 Method to reuse the pulse discharge energy during Li-ion fast charging for better power flow efficiency
A battery charger for charging a battery with voltage from an input supply and method for using are disclosed. The battery charger may comprise a power path...
US-1,018,6756 Antennas in electronic devices
In various embodiments, the disclosure describes systems and methods that can be use in connection with electronic devices (for example, mobile devices) and can...
US-1,018,6754 Antenna integrated into a touch sensor of a touchscreen display
A touch sensor with a transparent conductive layer and a metalized border area at least partially bordering the transparent conductive layer and forming a...
US-1,018,6747 Transformer based on-package power combiner
Embodiments are generally directed to a transformer based on-package power combiner. An embodiment of a power combiner includes multiple primary coils on a...
US-1,018,6735 Void filling battery
A battery cell is formed to efficiently use unoccupied space in an electronic device. The battery cell may be formed by disposing an electrically insulating...
US-1,018,6676 Emissive devices for displays
Embodiments related to emissive devices for displays are discussed. Some embodiments include light emitting diodes including an electron transport layer core...
US-1,018,6582 Graphene fluorination for integration of graphene with insulators and devices
Embodiments of the present disclosure describe multi-layer graphene assemblies including a layer of fluorinated graphene, dies and systems containing such...
US-1,018,6581 Group III-N nanowire transistors
A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a...
US-1,018,6580 Semiconductor device having germanium active layer with underlying diffusion barrier layer
Semiconductor devices having germanium active layers with underlying diffusion barrier layers are described. For example, a semiconductor device includes a gate...
US-1,018,6499 Integrated circuit package assemblies including a chip recess
IC package assemblies including a molding compound in which an IC chip surface is recessed relative to the molding compound. Thickness of the IC chip may be...
US-1,018,6497 Techniques and configurations to control movement and position of surface mounted electrical devices
Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices....
US-1,018,6484 Metal on both sides with clock gated-power and signal routing underneath
A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer...
US-1,018,6480 Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same
A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A ...
US-1,018,6465 Package-integrated microchannels
Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package...
US-1,018,6325 Method and apparatus for shielded read to reduce parasitic capacitive coupling
In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash...
US-1,018,6278 Microphone array noise suppression using noise field isotropy estimation
Noise is suppressed from a microphone array by estimating a noise field isotropy. In some examples audio is received from a plurality of microphones. A power...
US-1,018,6277 Microphone array speech enhancement
Speech received from a microphone array is enhanced. In one example, a noise filtering system receives audio from the plurality of microphones, determines a...
US-1,018,6236 Universal codec
Techniques related to coding data including techniques for coding data using a universal codec are generally described. In some examples, such techniques may...
US-1,018,6065 Technologies for motion-compensated virtual reality
Technologies for motion-compensated virtual reality include a virtual reality compute device of a vehicle. The virtual reality compute device is configured to...
US-1,018,6011 Programmable coarse grained and sparse matrix compute hardware with advanced scheduling
One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single...
US-1,018,6007 Adaptive scheduling for task assignment among heterogeneous processor cores
An example system for adaptive scheduling of task assignment among heterogeneous processor cores may include any number of CPUs, a graphics processing unit...
US-1,018,5842 Cache and data organization for memory protection
This disclosure is directed to cache and data organization for memory protection. Memory protection operations in a device may be expedited by organizing cache...
US-1,018,5818 Methods for generating random data using phase change materials and related devices and systems
Devices and systems operable to generate random numbers are disclosed and described. Such include an array of phase change material cells electrically coupled...
US-1,018,5813 Orientation aware authentication on mobile platforms
Systems and methods may provide for receiving an authentication input and determining an authentication orientation of a mobile platform during entry of the...
US-1,018,5696 Method for interface initialization using bus turn-around
An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a...
US-1,018,5695 Device, system and method for on-chip testing of protocol stack circuitry
Techniques and mechanisms for providing test functionality at an integrated circuit (IC) chip. In an embodiment, the IC chip includes protocol stacks variously...
US-1,018,5680 Secure direct memory access
Examples are disclosed for establishing a secure destination address range responsive to initiation of a direct memory access (DMA) operation. The examples also...
US-1,018,5633 Processor state integrity protection using hash verification
This disclosure is directed to processor state integrity protection using hash verification. A device may comprise processing circuitry and memory circuitry....
US-1,018,5619 Handling of error prone cache line slots of memory side cache of multi-level system memory
An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory...
US-1,018,5618 Method and apparatus for selecting one of a plurality of bus interface configurations to use
Provided are a method and apparatus for selecting one of a plurality of bus interface configurations to use. Selection is made of a first bus interface...
US-1,018,5567 Multilevel conversion table cache for translating guest instructions to native instructions
A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest...
US-1,018,5566 Migrating tasks between asymmetric computing elements of a multi-core processor
In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core...
US-1,018,5562 Conflict mask generation
Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can...
US-1,018,5547 Techniques for distributed operation of secure controllers
Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers...
US-1,018,5511 Technologies for managing an operational characteristic of a solid state drive
Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the...
US-1,018,5501 Method and apparatus for pinning memory pages in a multi-level system memory
An apparatus is described. The apparatus includes a memory controller to interface with a multi-level system memory. The memory controller includes a pinning...
US-1,018,5401 Determination of cursor position on remote display screen based on bluetooth angle of arrival
Systems, apparatuses and methods may determine the exact position of a cursor on the screen of a display device when the user is located at a predetermined...
US-1,018,5385 Method and apparatus to reduce idle link power in a platform
A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform...
US-1,018,5382 Multiple voltage identification (VID) power architecture, a digital synthesizable low dropout regulator, and...
Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external...
US-1,018,5349 Apparatus and method for extending frequency range of a circuit and for over-clocking or under-clocking
Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having...
US-1,018,4983 Interface independent test boot method and apparatus using automatic test equipment
Computer device(s), apparatus(es), and methods enable and/or perform interface independent test boot of a System on Chip (SoC). A test Direct Memory Access...
US-1,018,4977 Devices and methods for testing integrated circuits
An integrated circuit includes a first power unit, a second power unit, and a selection switch. The first power unit generates a first output voltage and is...
US-1,018,4961 Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator
Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with...
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