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| Patent # | Description |
|---|---|
| US-9,646,952 |
Microelectronic package debug access ports A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,... |
| US-9,646,910 |
Integrated heat spreader that maximizes heat transfer from a multi-chip
package In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed... |
| US-9,646,903 |
Thermoset polymides for microelectronic applications Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the... |
| US-9,646,890 |
Replacement metal gates to enhance transistor strain Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain. |
| US-9,646,856 |
Method of manufacturing a semiconductor device including removing a relief
layer from back surface of... A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad... |
| US-9,646,854 |
Embedded circuit patterning feature selective electroless copper plating Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more... |
| US-9,646,851 |
Embedded semiconductive chips in reconstituted wafers, and systems
containing same A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are... |
| US-9,646,822 |
Active regions with compatible dielectric layers A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure... |
| US-9,646,720 |
Self-repair logic for stacked memory architecture Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a... |
| US-9,646,660 |
Selectable memory access time The present disclosure relates to selectable memory access time. An apparatus includes a memory controller. The memory controller is configured to select a... |
| US-9,646,657 |
Power loss capacitor test using voltage ripple These present disclosure provides techniques to determine the capacitance of a power loss capacitor based on voltage ripple. The power loss capacitor may be a... |
| US-9,646,630 |
Voice recognition via wide range adaptive beam forming and multi-channel
audio data An apparatus, system, and computer readable media for data pre-processing and processing for voice recognition are described herein. The apparatus includes... |
| US-9,646,570 |
Mechanism for facilitating improved copying of graphics data on computing
devices A mechanism is described for facilitating improved copying of graphics data at computing devices according to one embodiment. A method of embodiments, as... |
| US-9,646,522 |
Enhanced information delivery using a transparent display Information is delivered about a particular external environment using a transparent display. In one embodiment, a method includes determining a position of a... |
| US-9,646,426 |
Methods and devices for determining a location estimate Generally discussed herein are systems and apparatuses for managing a plurality of location providers and/or assigning a location provider to provide a location... |
| US-9,646,216 |
Multiple user biometric for authentication to secured resources Various embodiments are generally directed to the provision and use of multiple person biometric authentication systems. An apparatus including a processor... |
| US-9,646,153 |
Securing content from malicious instructions A method and system is provided for securing content from malicious shaders. The method includes determining the content the shader is to execute. A signature... |
| US-9,646,144 |
Extending user authentication across a trust group of smart devices Particular embodiments described herein provide for a wearable electronic device with a biometric sensor and logic. At least a portion of the logic is... |
| US-9,645,965 |
Apparatus, system, and method for improving equalization with a hardware
driven algorithm A system and method comprising, in response to a first component and a link partner of the first component, undergoing equalization, the first component is to... |
| US-9,645,942 |
Method for pinning data in large cache in multi-level memory system A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The... |
| US-9,645,939 |
Hardware apparatuses and methods for distributed durable and atomic
transactions in non-volatile memory Hardware apparatuses and methods for distributed durable and atomic transactions in non-volatile memory are described. In one embodiment, a hardware apparatus... |
| US-9,645,938 |
Cache operations for memory management In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile... |
| US-9,645,930 |
Dynamic home tile mapping Technologies for dynamic home tile mapping are described. an address request can be received from a processing core, the processing core being associated with a... |
| US-9,645,884 |
Performing a cyclic redundancy checksum operation responsive to a
user-level instruction In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data... |
| US-9,645,864 |
Technologies for operating system transitions in multiple-operating-system
environments Technologies for transitioning between operating systems include a computing device having a main memory and a data storage device. The computing device... |
| US-9,645,829 |
Techniques to communicate with a controller for a non-volatile dual
in-line memory module Examples may include communicating with a controller for a non-volatile dual in-line memory module through a system management bus (SMBus) interface. In some... |
| US-9,645,826 |
Coalescing adjacent gather/scatter operations According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first... |
| US-9,645,821 |
Instruction and logic for processing text strings A processor includes a decoder logic to decode a compare instruction, and an execution unit to execute the compare instruction. The compare instruction is to... |
| US-9,645,820 |
Apparatus and method to reserve and permute bits in a mask register An apparatus and method are described for performing a bit reversal and permutation on mask values. For example, a processor is described to execute an... |
| US-9,645,819 |
Method and apparatus for reducing area and complexity of instruction
wakeup logic in a multi-strand... A computer system, a computer processor and a method executable on a computer processor involve placing each sequence of a plurality of sequences of computer... |
| US-9,645,743 |
Selective I/O prioritization by system process/thread Systems, methods, and apparatus to identify and prioritize application processes in one or more subsystems. Some embodiments identifying applications and... |
| US-9,645,739 |
Host-managed non-volatile memory One embodiment provides a computing device. The computing device includes a processor; a chipset; a memory; and indirection logic. The indirection logic is to... |
| US-9,645,646 |
Three dimensional contextual feedback wristband device A device to output two or more coordinated haptic effects, comprising, a first haptic effect generator to output a first haptic effect, a second haptic effect... |
| US-9,645,472 |
Magnetic fluid shutter operation Techniques related to a method, apparatus, and systems for magnetic fluid shutter operation are described herein. For example, an apparatus may include an... |
| US-9,645,242 |
Device, system and method of collaborative location error correction Some demonstrative embodiments include devices, systems and/or methods of collaboratively correct location errors. For example, a device may include a... |
| US-9,642,556 |
Subcutaneously implantable sensor devices and associated systems and
methods Methods of using subcutaneously implantable sensor devices and associated systems having a communication module that is controlled based upon the detection of a... |
| US-9,642,248 |
Microelectronic structures having laminated or embedded glass routing
structures for high density packaging Embodiments of the present description relate to the field of fabricating microelectronic structures. The microelectronic structures may include a glass routing... |
| US-9,642,084 |
Methods and arrangements to offload scans of a large scan list Embodiments describe arrangements related to offload scanning of large scan lists. Embodiments may comprise logic such as hardware and/or code to facilitate... |
| US-9,642,006 |
Secure wireless charging An embodiment includes a method executed by at least one processor of a member computing node comprising: establishing a communication channel with a verifier... |
| US-9,640,880 |
Cable connector A cable connector that includes a substrate having a plurality of conductive pads and at least one grounding pad. The cable connector further includes twin... |
| US-9,640,646 |
Semiconductor device having group III-V material active region and graded
gate dielectric Semiconductor devices having group III-V material active regions and graded gate dielectrics and methods of fabricating such devices are described. In an... |
| US-9,640,622 |
Selective epitaxially grown III-V materials based devices A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V... |
| US-9,640,537 |
Non-silicon device heterolayers on patterned silicon substrate for CMOS by
combination of selective and... A single fin or a pair of co-integrated n- and p- type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one... |
| US-9,639,490 |
Ring protocol for low latency interconnect switch Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed... |
| US-9,639,134 |
Method and apparatus to provide telemetry data to a power controller of a
processor In an embodiment, a processor includes a plurality of cores including a first core. The first core includes a first plurality of accumulator logics, each... |
| US-9,639,133 |
Accurate power-on detector Described is an apparatus which comprises: an input for providing a first voltage signal; a level translator, coupled to the input, to translate the first... |
| US-9,635,655 |
Enhancement to the buffer status report for coordinated uplink grant
allocation in dual connectivity in an LTE... Technology for efficiently splitting a bearer at the packet data convergence protocol (PDCP) layer for uplink (UL) data transfers in wireless networks where... |
| US-9,635,530 |
User equipment (UE) supporting packet-switched emergency calls over IP
multimedia subsystem (IMS) Embodiments of a mobile device, a User Equipment (UE), and method for supporting emergency calls on a packet-switched network are generally described herein. In... |
| US-9,634,124 |
Interlayer dielectric for non-planar transistors The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a... |
| US-9,633,983 |
Semiconductor chip stacking assemblies Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second... |
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