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Patent # Description
US-9,819,479 Digitally controlled two-points edge interpolator
Described herein are technologies related to an implementation of a digital-to-time converter (DTC) circuitry that utilizes a first interpolation and a second...
US-9,819,452 Efficient link layer retry protocol utilizing implicit acknowledgements
Methods, apparatus, and systems for implementing a link layer retry protocol utilizing implicit ACKnowledgements (ACKs). Peer link interfaces are configured to...
US-9,819,442 Internal interference signaling
In accordance with an illustrative embodiment, a method and device are provided. The method, system, and device comprise an information module and a...
US-9,819,401 Highly selective low-power card detector for near field communications (NFC)
Described herein are architectures, platforms and methods for implementing low-power detection of a near field communication (NFC) card or tags. In particular,...
US-9,819,386 Methods and arrangements to increase transmission range
Logic may transmit or receive communications that hop frequencies in response to trigger events across a large bandwidth. Logic may generate a communication...
US-9,819,362 Apparatus and method for detecting and mitigating bit-line opens in flash memory
Described is a method which comprises performing a first read from a portion of a non-volatile memory, the first read to provide a first codeword; decoding the...
US-9,819,356 Injection locked ring oscillator based digital-to-time converter and method for providing a filtered...
Apparatus and methods for a digital-to-time converter (DTC) are provided. In an example, a DTC can include a phase interpolator and a ring oscillator. The phase...
US-9,819,327 Bulk acoustic wave resonator tuner circuits
Techniques and configurations are disclosed for bulk acoustic wave resonator (BAWR) tuner circuits and their use in integrated circuit (IC) packages and mobile...
US-9,819,311 Apparatus and a method for providing a supply control signal for a supply unit
An apparatus for providing a supply control signal for a supply unit, the supply unit being configured to provide a variable controlled power supply to the...
US-9,819,266 Digitally controlled zero current switching
Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry and zero crossing logic circuitry. The switch controller...
US-9,819,258 Systems and methods for latch-up detection and mitigation
Systems and methods for latch-up detection and mitigation. One aspect includes a method implemented in a system divided into a plurality of power blocks, where...
US-9,819,253 MEMS device
According to the present invention there is provided a device comprising a MEMS die and, a single magnet, wherein the MEMS die cooperates with the magnet, such...
US-9,819,122 Apparel compute device connection
System and techniques for an apparel compute device connection are described herein. A base for a removable apparel compute device is bonded to a garment. The...
US-9,819,079 Modular antenna for near field coupling integration into metallic chassis devices
Described herein are techniques related to near field communication and wireless power transfers. A portable device may include a modular antenna that offers...
US-9,818,933 6F2 non-volatile memory bitcell
An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one...
US-9,818,884 Strain compensation in transistors
An embodiment includes a device comprising: a first epitaxial layer, coupled to a substrate, having a first lattice constant; a second epitaxial layer, on the...
US-9,818,870 Transistor structure with variable clad/core dimension for stress and bandgap
An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first...
US-9,818,864 Vertical nanowire transistor with axially engineered semiconductor and gate metallization
Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In...
US-9,818,847 Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate...
A high-k gate dielectric interface with a group III-V semiconductor surface of a non-planar transistor channel region is non-directionally doped with nitrogen....
US-9,818,751 Methods of forming buried vertical capacitors and structures formed thereby
Methods of forming passive elements under a device layer are described. Those methods and structures may include forming at least one passive structure, such as...
US-9,818,719 Bumpless build-up layer package design with an interposer
The present disclosure relates to the field of integrated circuit package design and, more particularly, to packages using a bumpless build-up layer (BBUL)...
US-9,818,710 Anchored interconnect
An embodiment includes a semiconductor structure comprising: a backend portion including a plurality of metal layers between bottom and top metal layers; the...
US-9,818,672 Flow diversion devices
Embodiments of flow diversion devices (FDDs) are disclosed herein. An FDD may include a body formed of a body material and a plurality of thermally deformable...
US-9,818,460 Negative bitline write assist circuit and method for operating the same
A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write...
US-9,818,458 Techniques for entry to a lower power state for a memory device
Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device...
US-9,818,457 Extended platform with additional memory module slots per CPU socket
Electronic devices and methods including a printed circuit board configured to accept CPUs and memory modules are described. One apparatus includes a printed...
US-9,818,427 Automatic self-utterance removal from multimedia files
Embodiments of a system and method for removing speech by a user from audio frames are generally described herein. A method may include receiving a plurality of...
US-9,818,414 Dialogue system with audio watermark
Described is an apparatus which comprises: first logic to generate a first audio data and to embed the first audio data with a watermark to generate an embedded...
US-9,818,404 Environmental noise detection for dialog systems
Embodiments are directed to receiving a speech signal representative of audible speech, processing the speech signal to interpret the speech signal by a dialog...
US-9,818,166 Graph-based application programming interface architectures with producer/consumer nodes for enhanced image...
A flexible representation of fine grain image buffer validity is included in an image graph implementation API to provide a mechanism for a graph node developer...
US-9,818,162 Socially and contextually appropriate recommendation systems
Systems and methods may provide for conducting an interest analysis of data associated with a user, wherein the interest analysis distinguishes between abstract...
US-9,818,032 Automatic video summarization
System and techniques for automatic video summarization are described herein. A video may be obtained and a semantic model of the video may be generated from...
US-9,817,976 Techniques for detecting malware with minimal performance degradation
Various embodiments are generally directed to techniques for detecting malware in a manner that mitigates the consumption of processing and/or storage resources...
US-9,817,964 Methods and apparatus to facilitate secure screen input
Methods, apparatus, systems and articles of manufacture are disclosed to facilitate secure screen input. An example disclosed system includes a user interface...
US-9,817,959 Wearable electronic devices
Wearable electronic device technology is disclosed. In an example, a wearable electronic device can include a handling portion that facilitates donning the...
US-9,817,787 Method, apparatus and system for encapsulating information in a communication
In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one...
US-9,817,770 Memory address re-mapping of graphics data
A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating...
US-9,817,758 Instructions to mark beginning and end of non transactional code region requiring write back to persistent storage
A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified...
US-9,817,738 Clearing poison status on read accesses to volatile memory regions allocated in non-volatile memory
Systems and methods may provide for detecting that a read operation is directed to a memory region while the memory region is in a poisoned state and clearing...
US-9,817,714 Memory device on-die error checking and correcting code
In a system where a memory device performs on-die ECC, the ECC operates on N-bit data words as two (N/2)-bit segments, with a code matrix having a corresponding...
US-9,817,684 Cross-function virtualization of a telecom core network
In the present disclosure, functions associated with the central office of an evolved packet core network are co-located onto a computer platform or...
US-9,817,673 Technologies for fast low-power startup of a computing device
Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device...
US-9,817,666 Method for a delayed branch implementation by using a front end track table
A method for a delayed branch implementation by using a front end track table. The method includes receiving an incoming instruction sequence using a global...
US-9,817,644 Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic region
An apparatus and method is described herein for conditionally committing and/or speculative checkpointing transactions, which potentially results in dynamic...
US-9,817,642 Apparatus and method for efficient call/return emulation using a dual return stack buffer
An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. An embodiment of a processor includes: a dual return stack...
US-9,817,634 Distinguishing speech from multiple users in a computer interaction
Speech from multiple users is distinguished. In one example, an apparatus has a sensor to determine a position of a speaker, a microphone array to receive audio...
US-9,817,600 Configuration information backup in memory systems
According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status...
US-9,817,540 Device, system, and method of composing logical computing platforms
Device, system, and method of composing logical computing platforms. For example, a wireless computing device includes: one or more wireless transceivers to...
US-9,817,500 Mechanism for facilitating flexible wraparound displays for computing devices
A mechanism is described for facilitating flexible wraparound displays at computing devices according to one embodiment. A method of embodiments, as described...
US-9,817,403 Enabling dynamic sensor discovery in autonomous devices
Systems, apparatuses, and methods for enabling sensor discovery in autonomous devices herein. An example system for enabling dynamic sensor discovery including...
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