Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: intel





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,911,815 Extended-drain structures for high voltage field effect transistors
Planar and non-planar field effect transistors with extended-drain structures, and techniques to fabricate such structures. In an embodiment, a field plate...
US-9,911,807 Strain compensation in transistors
Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The...
US-9,911,723 Magnetic small footprint inductor array module for on-package voltage regulator
An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements...
US-9,911,694 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed...
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to...
US-9,911,689 Through-body-via isolated coaxial capacitor and techniques for forming same
Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor...
US-9,911,509 Counter to locate faulty die in a distributed codeword storage system
Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment,...
US-9,911,386 Efficient luminous display
In one embodiment a display assembly comprises a liquid crystal module, a backlight assembly comprising an array of light emitting diodes, a timing controller,...
US-9,911,219 Detection, tracking, and pose estimation of an articulated body
Techniques related to pose estimation for an articulated body are discussed. Such techniques may include extracting, segmenting, classifying, and labeling...
US-9,911,107 Automated secure check-out and drop-off return of products using mobile device
Generally, this disclosure describes a method and system for automated check-out and drop-off return of products using a mobile device. A method may include...
US-9,910,972 Remote trust attestation and geo-location of servers and clients in cloud computing environments
Methods and systems may provide for selecting a hypervisor protocol from a plurality of hypervisor protocols based on a communication associated with a remote...
US-9,910,814 Method, apparatus and system for single-ended communication of transaction layer packets
Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated...
US-9,910,809 High performance interconnect link state transitions
A supersequence is sent to another device to indicate a transition from a partial width link state to another active link state. The supersequence is to be sent...
US-9,910,807 Ring protocol for low latency interconnect switch
Methods, systems, and apparatus for implementing low latency interconnect switches between CPU's and associated protocols. CPU's are configured to be installed...
US-9,910,796 Programmable event driven yield mechanism which may activate other threads
Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes...
US-9,910,793 Memory encryption engine integration
Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a...
US-9,910,792 Composite field scaled affine transforms-based hardware accelerator
A processing system includes a memory and a cryptographic accelerator operatively coupled to the memory. The cryptographic accelerator performs a split...
US-9,910,790 Using a memory address to form a tweak key to use to encrypt and decrypt data
Provided are a memory system, memory controller, and method for using a memory address to form a tweak key to use to encrypt and decrypt data. A base tweak co...
US-9,910,786 Efficient redundant array of independent disks (RAID) write hole solutions
Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power...
US-9,910,771 Non-volatile memory interface
In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a...
US-9,910,728 Method and apparatus for partial cache line sparing
Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having...
US-9,910,721 System and method for execution of application code compiled according to two instruction set architectures
Methods, apparatuses and storage medium associated with execution of application code having multiple ISAs, are disclosed. In various embodiments, a runtime...
US-9,910,699 Virtual processor direct interrupt delivery mechanism
A method comprising is described. The method includes receiving an interrupt targeting a virtual processor, determining a status of the virtual processor and...
US-9,910,692 Enhanced virtual function capabilities in a virtualized network environment
The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and...
US-9,910,670 Instruction set for eliminating misaligned memory accesses during processing of an array having misaligned data...
A processor is described having an instruction execution pipeline. The instruction execution pipeline includes an instruction fetch stage to fetch an...
US-9,910,669 Instruction and logic for characterization of data access
A processor includes a front end to receive an instruction, a decoder to decode the instruction, a core to execute the first instruction, and a retirement unit...
US-9,910,650 Method and apparatus for approximating detection of overlaps between memory ranges
A computer-implemented method for managing loop code in a compiler includes using a conflict detection procedure that detects across-iteration dependency for...
US-9,910,646 Technologies for native code invocation using binary analysis
Technologies for native code invocation using binary analysis are described. A computing device for invoking native code from managed code using binary analysis...
US-9,910,611 Access control for memory protection key architecture
A processing system includes a processing core to execute a task and a memory management unit, coupled to the core. The memory management unit includes a...
US-9,910,604 Refresh parameter-dependent memory refresh management
Apparatus, systems, and methods to manage memory refresh operations are described. In one embodiment, an electronic device comprises a processor and memory...
US-9,910,498 System and method for close-range movement tracking
A system and method for close range object tracking are described. Close range depth images of a user's hands and fingers or other objects are acquired using a...
US-9,910,484 Voltage regulator training
Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system....
US-9,910,483 Distribution of tasks among asymmetric processing elements
Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate...
US-9,910,481 Performing power management in a multicore processor
In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance...
US-9,910,475 Processor core power event tracing
A processor includes a trace unit to monitor activity by the processor and generate trace packets indicative of the activity by the processor. The trace packets...
US-9,910,470 Controlling telemetry data communication in a processor
In one embodiment, a processor includes cores to execute instructions. At least some of the cores include a telemetry data control logic to send a first...
US-9,910,270 Electro-mechanical designs for MEMS scanning mirrors
Electro-mechanical designs for MEMS scanning mirrors are described. In various embodiments, a driving coil may be situated on a reflective portion of a MEMS...
US-9,905,126 Home environment management method and apparatus
Embodiments of the present disclosure provide techniques and configurations for a system to manage a home environment. In one instance, an apparatus for...
US-9,905,046 Mapping multi-rate shading to monolithic programs
In multi-rate shading, a coarse-rate shading phase is added on top of existing pixel-rate phase to significantly improve performance with minimum impact to...
US-9,904,632 Technique for supporting multiple secure enclaves
A technique to enable secure application and data integrity within a computer system. In one embodiment, one or more secure enclaves are established in which an...
US-9,904,547 Packed data rearrangement control indexes generation processors, methods, systems and instructions
A method of an aspect includes receiving a packed data rearrangement control indexes generation instruction. The packed data rearrangement control indexes...
US-9,904,546 Instruction and logic for predication and implicit destination
A processor includes a front end to receive an instruction. The processor also includes a core to execute the instruction. The core includes logic to execute a...
US-9,904,513 Handling instructions that require adding results of a plurality of multiplications
Floating point compound equations that involve addition of at least three terms, where each term involves a multiplication, can be implemented by using a bypass...
US-9,904,349 Technologies for managing power of an embedded controller during a low-power state
Technologies for managing the power usage of components of a computing device, while the components and the computing device are in a low-power state, such as a...
US-9,904,027 Rack assembly structure
Embodiments of the present disclosure provide techniques and configurations for a rack assembly. In one embodiment, a tray to be disposed in a rack assembly may...
US-9,902,340 Systems, methods, and apparatus for enhancing a camera field of view in a vehicle
Certain embodiments of the invention may include systems, methods, and apparatus for enhancing a field of view of a camera in a vehicle. According to an example...
US-9,902,152 Piezoelectric package-integrated synthetic jet devices
Embodiments of the invention include a piezoelectric package integrated jet device. In one example, the jet device includes a vibrating membrane positioned...
US-D811,417 Keyboard
US-9,900,983 Modular printed circuit board electrical integrity and uses
Modular printed circuit board (PCB) structures and methods of producing them are described herein. In some embodiments, a PCB structure may include a first PCB...
US-9,900,906 Method, apparatus, and computer readable medium for multi-user scheduling in wireless local-area networks
Methods, apparatuses, and computer readable media are shown for multi-user scheduling in wireless local-area networks (WLANs). A wireless communication device...
US-9,900,881 eNodeB and UE for dynamic cell on and off
Disclosed in some examples are methods, systems, and machine readable mediums which reuse existing LTE functionality to rapidly signal UEs on the availability...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.