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Patent # Description
US-1,017,5992 Systems and methods for enhancing BIOS performance by alleviating code-size limitations
Systems and methods are disclosed for initialization of a processor. Embodiments relate to alleviating any BIOS code size limitation. In one example, a system...
US-1,017,5990 Gathering and scattering multiple data elements
According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer...
US-1,017,5986 Stateless capture of data linear addresses during precise event based sampling
A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution...
US-1,017,5944 Mixed-precision floating-point arithmetic circuitry in specialized processing blocks
The present embodiments relate to integrated circuits with circuitry that efficiently performs mixed-precision floating-point arithmetic operations. Such...
US-1,017,5903 N plane to 2N plane interface in a solid state drive (SSD) architecture
A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a...
US-1,017,5806 Touchscreen for use with flexible display
Particular embodiments described herein provide for an electronic device, that includes a circuit board coupled to a plurality of electronic components (which...
US-1,017,5744 Link power savings with state retention
Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a...
US-1,017,5740 Mapping a performance request to an operating frequency in a processor
In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of...
US-1,017,5716 Technologies for low-power and high-accuracy timestamps
Technologies for low-power and high-accuracy timestamps are disclosed. A compute device may have a sensor hub to capture sensor data with a corresponding...
US-1,017,5655 Time-to-digital converter
An apparatus is provided which comprises: a first clock line to provide a first clock; a second clock line to provide a second clock; a delay line having a...
US-1,017,5296 Testing a board assembly using test cards
A testing arrangement is provided which comprises: a board assembly comprising (i) a first connector configured to receive a first component while the board...
US-1,017,5190 Highly selective coated-electrode nanogap transducers for the detection of redox molecules
Highly selective coated-electrode nanogap transducers for the detection of redox molecules are described. In an example, an analyte detection system includes...
US-1,017,2432 Applicator for semi-solid materials
An applicator for a stick product, such as lip balm, has a generally tubular housing closed at one end by an elastomeric base cap and at the other by an end...
US-1,017,2164 Spatial reuse with training in RTS-CTS
Computing readable media, apparatuses, and methods for spatial reuse with training in RTS-CTS are disclosed. An apparatus comprising processing circuitry is...
US-1,017,2143 Second order intermodulation cancelation for RF transceivers
A method includes estimating a transmit leakage signal for a duplexer, where the duplexer is included in a transceiver that includes a transmit chain and a...
US-1,017,2127 Early termination of repeated transmissions for MTC
Systems, apparatus, user equipment (UE), evolved node B(eNB), and methods are described for machine-type communications (MTC) with early termination of repeated...
US-1,017,2099 Methods and arrangements to coordinate communications in a wireless network
Logic may comprise hardware and/or code to coordinate communications of wireless communications devices to reduce power consumption by stations. Logic may...
US-1,017,1982 Emergency evacuation service
Various systems and methods for providing an emergency evacuation service are described herein. An apparatus to provide an emergency evacuation service...
US-1,017,1808 In-loop adaptive wiener filter for video coding and decoding
A video encoder may use an adaptive Wiener filter inside the core video encoding loop to improve coding efficiency. In one embodiment, the Wiener filter may be...
US-1,017,1592 Techniques for multi-level service discovery
Examples are disclosed for multi-level service discovery. In some examples, a first level of information indicating a service type for a service provided by a...
US-1,017,1500 Systems, apparatuses, and methods for enforcing security on a platform
Embodiments of a system, apparatus, and method of platform security are describe. In some embodiments, a system comprises a manageability engine to detect if a...
US-1,017,1420 Spatial reuse for uplink multiuser transmissions
Methods, apparatuses, computer readable media for spatial reuse for uplink multi-user transmissions. An apparatus of a station comprising processing circuitry...
US-1,017,1272 Computationally efficient algorithm for mitigating phase noise in OFDM receivers
An inter-carrier interference (ICI) mitigation circuit associated with an orthogonal frequency division multiplexing (OFDM) receiver is disclosed. The ICI...
US-1,017,1232 Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes...
US-1,017,1231 Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes...
US-1,017,1213 Communication device and method for performing radio communication
A communication device is provided that includes a radio frequency circuit configured to receive and transmit radio frequency signals. The communication device...
US-1,017,1168 Optoelectronic transceiver with power management
Embodiments herein relate to optoelectronic transceivers with power management. An optoelectronic device may include a photodetector, a loss of signal (LOS)...
US-1,017,1149 Apparatus, system and method of wireless backhaul and access communication via a common antenna array
Some demonstrative embodiments include apparatuses, systems and/or methods of wireless backhaul and access communication via a common antenna array. For...
US-1,017,1126 Apparatus for uplink multi-antenna communication based on a hybrid coupler and a tunable phase shifter
Embodiments of front-end module (FEM) circuitry and a communication device are generally described herein. In some embodiments, the FEM circuitry may be...
US-1,017,1033 Crystal oscillator interconnect architecture with noise immunity
An apparatus is provided which comprises: a crystal having an input and an output; a first interconnect line having first and second ends, wherein the first end...
US-1,017,0612 Epitaxial buffer layers for group III-N transistors on silicon substrates
Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon...
US-1,017,0428 Cavity generation for embedded interconnect bridges utilizing temporary structures
Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes...
US-1,017,0409 Package on package architecture and method for making
Embodiments of the present disclosure are directed to package assemblies and methods for fabricating package assemblies. In one embodiment, a package assembly...
US-1,017,0314 Pulsed laser anneal process for transistor with partial melt of a raised source-drain
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack...
US-1,017,0244 Fabrication of porous silicon electrochemical capacitors
Methods of forming microelectronic structures are described. Embodiments of those methods may include forming an electrochemical capacitor device by forming...
US-1,017,0185 Hybrid memory and MTJ based MRAM bit-cell and array
Described is an apparatus for a hybrid eDRAM and MRAM memory cell comprising: a capacitor having a first terminal and a second terminal; a first transistor...
US-1,017,0165 Multiple register memory access instructions, processors, methods, and systems
A processor includes N-bit registers and a decode unit to receive a multiple register memory access instruction. The multiple register memory access instruction...
US-1,017,0135 Audio gait detection and identification
Systems, apparatuses and methods for technology to perform gait detection and identification. The system includes a pre-processing pipeline to process audio...
US-1,017,0134 Method and system of acoustic dereverberation factoring the actual non-ideal acoustic environment
A system, article, and method of acoustic dereverberation factoring the actual non-ideal acoustic environment.
US-1,017,0115 Linear scoring for low power wake on voice
Key phrase detection techniques for applications such as wake on voice are discussed include performing a vectorized operation on a multiple element acoustic...
US-1,016,9920 Virtual guard rails
A method for virtual guard rail implementation includes collecting user parameters, representing user limitations, for a computer simulation executed by a...
US-1,016,9907 Multi mode texture sampler for flexible filtering of graphical texture data
For a given texture address, a texture sampler fetches and reduces texture data with a filter accumulator suitable for providing a weighted average over a...
US-1,016,9574 Using trusted execution environments for security of code and data
An embodiment includes a processor coupled to memory to perform operations comprising: creating a first trusted execution environment (TXE), in protected...
US-1,016,9558 Enhancing biometric security of a system
In one embodiment, a method includes receiving an ordered sequence of biometric inputs from a user via a biometric sensor, determining if each of the ordered...
US-1,016,9518 Methods for delaying register reset for retimed circuits
An integrated circuit design may include registers and combinational logic. The registers may be reset using an original reset sequence. Integrated circuit...
US-1,016,9296 Distributed matrix multiplication for neural networks
In one embodiment, a matrix operation associated with a plurality of input matrices may be performed. The plurality of input matrices may be partitioned into a...
US-1,016,9269 Architecture and method for managing interrupts in a virtualized environment
A method may comprise identifying a signal indicating real-time mode operation for a guest operating system (OS) and directly routing an interrupt for a first...
US-1,016,9268 Providing state storage in a processor for system management mode
In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state...
US-1,016,9254 Increasing virtual-memory efficiencies
Embodiments of techniques and systems for increasing efficiencies in computing systems using virtual memory are described. In embodiments, instructions which...
US-1,016,9245 Latency by persisting data relationships in relation to corresponding data in persistent memory
A processor or system may include a memory controller to store, in a pre-allocated portion of bit-addressable, random access persistent memory (PM), a...
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