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Secure replay protected storage
Embodiments of the invention create an underlying infrastructure in a flash memory device (e.g., a serial peripheral interface (SPI) flash memory device) such...
Instruction and logic for adaptive dataset priorities in processor caches
A processor includes a front end, a cache, and a cache controller. The front end includes logic to receive an instruction defining a priority dataset. The...
Apparatus and method for accelerating operations in a processor which uses
shared virtual memory
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an...
Method, apparatus, system for handling address conflicts in a distributed
memory fabric architecture
Method, apparatus and system for handling address conflicts in distributed memory fabrics. Memory access requests originating from caching agents and...
Method, apparatus and system for handling cache misses in a processor
In an embodiment, a processor includes one or more cores, and a distributed caching home agent (including portions associated with each core). Each portion...
Workload adaptive address mapping
Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request...
Register error protection through binary translation
Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on...
Electronic device to provide notification of event
An electronic device may be provided that includes logic, at least partially implemented in hardware, to detect an occurrence of a blocking instance at the...
Synchronizing multiple threads efficiently
In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to...
Low latency virtual machine page table management
Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views...
Virtualization event processing in a layered virtualization architecuture
Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an...
Method, device and system for controlling execution of an instruction
sequence in a data stream accelerator
Techniques and mechanisms for controlling execution of an instruction sequence in a data stream processing engine. In an embodiment, a control unit of the data...
Creating an isolated execution environment in a co-designed processor
In an embodiment, a processor includes a binary translation (BT) container having code to generate a binary translation of a first code segment and to store the...
Register allocation for rotation based alias protection register
A system may comprise an optimizer/scheduler to schedule on a set of instructions, compute a data dependence, a checking constraint and/or an anti-checking...
Method and apparatus for cutting senior store latency using store
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for cutting senior store latency...
Providing vector sub-byte decompression functionality
Methods, apparatus, instructions and logic provide SIMD vector sub-byte decompression functionality. Embodiments include shuffling a first and second byte into...
Functional unit having tree structure to support vector sorting algorithm
and other algorithms
An apparatus is described having a functional unit of an instruction execution pipeline. The functional unit has a plurality of compare-and-exchange circuits...
Apparatus and method of execution unit for calculating multiple rounds of
a skein hashing algorithm
An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a)...
Method and system for maintaining release consistency in shared memory
A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in...
Reducing power consumption of uncore circuitry of a processor
In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a...
Performing frequency coordination in a multiprocessor system
In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption...
Constraining processor operation based on power envelope information
In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a...
Apparatus and method to implement power management of a processor
In an embodiment, a processor includes a plurality of cores grouped into a plurality of clusters. The clusters are formed based on a corresponding operating...
Electronic device with improved power management and user experience
Particular embodiments described herein provide for an electronic device, such as a notebook computer, laptop, or tablet that includes a circuit board coupled...
MEMS micro-mirror assembly
A MEMS micro-mirror assembly (250, 300, 270, 400) comprising, a MEMS device (240) which comprises a MEMS die (241) and a magnet (231); a flexible PCB board...
Embodiments of the present disclosure are directed toward techniques and configurations for an apparatus with an optical connector. In one embodiment, the...
Communication station and method for time-of-flight positioning using
Embodiments of a communication station and method for time-of-flight (ToF) positioning in a wireless network are generally described herein. In some...
Convertible ultrabook device with a dual-sided, transparent touch screen
Methods to transport internet traffic over multiple wireless networks
A wireless communication device includes at least two transceivers and a processor. A respectively selected portion of a downlink and uplink data flow signals...
Enhanced physical downlink control channel scrambling and demodulation
reference signal sequence generation
Methods, apparatuses, and systems are described to provide enhanced physical downlink control channel scrambling and demodulation reference signal sequence...
Distributed antenna system and method for enhanced positioning
Embodiments of a distributed antenna system (DAS) and method for enhanced positioning in a wireless network are generally described herein. In some embodiments,...
Mechanisms for roaming between 3GPP operators and WLAN service providers
Embodiments describe methods, apparatuses and logic for a user equipment (UE) to connect to an access point (AP) in a wireless local area network (WLAN) based...
Method for exchanging strong encryption keys between devices using
alternate input methods in wireless personal...
A method for exchanging strong encryption keys between devices using alternate input methods. At least two devices that want to communicate with one another are...
Native medium access control support for beamforming
Apparatuses, systems, and methods that enable native MAC support of beamforming are contemplated. An embodiment may comprise a mobile computing device, such as...
Micropolygon splatting may involve tessellating by subdividing a mesh until triangle edges are shorter than 0.75 pixels. In some cases, rasterizing the...
Method and system using a data-driven model for monocular face tracking
A method and system using a data-driven model for monocular face tracking are disclosed, which provide a versatile system for tracking three-dimensional (3D)...
Mechanisms for locking computing devices
Various systems and methods for locking computing devices are described herein. In an example, a portable device comprises an electro-mechanical lock; and a...
Shared virtual memory
Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model...
Read and write masks update instruction for vectorization of recursive
computations over interdependent data
A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor...
Multimodal haptic effect system
A device to output a haptic effect includes a haptic effect generator comprising one or more microdroplets of a fluid configured to output a haptic effect, and...
Method, apparatus, and system for energy efficiency and energy
conservation including autonomous hardware-based...
Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of...
Integrated circuit test temperature control mechanism
A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target...
Systems and methods for detection of magnetic and motion-based landmarks
A method of determining landmarks includes receiving, at a computing system, a plurality of potential landmark measurements and corresponding signal...
Dual epoxy dielectric and photosensitive solder mask coatings, and
processes of making same
A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting...
Communication terminal and method for using a communication service
A communication terminal is described including a transceiver, a plurality of subscriber identity modules, wherein the transceiver is configured to receive a...
System and method for managing multiradio communications in a single
An apparatus may include a processor circuit and a communication scheduling module operable on the processor circuit to receive a first set of terminal...
Communication terminal and a method for reporting a channel quality
A communication terminal comprising a determiner configured to determine whether a communication service used by the communication terminal via a communication...
Enhanced physical downlink control channel (ePDCCH) inter-cell
interference coordination (ICIC)
Technology for communicating enhanced physical downlink control channels (ePDCCHs) configured for inter-cell interference coordination (ICIC) for a plurality of...
Link adaptation in coordinated multipoint system
Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for link adaptation within coordinated...
Performing multiple timing advance adjustments in a carrier aggregation
Technology for performing multiple timing advances in a carrier aggregation communication system is disclosed. A method comprises communicating a random access...