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Patent # Description
US-1,018,5633 Processor state integrity protection using hash verification
This disclosure is directed to processor state integrity protection using hash verification. A device may comprise processing circuitry and memory circuitry....
US-1,018,5619 Handling of error prone cache line slots of memory side cache of multi-level system memory
An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory...
US-1,018,5618 Method and apparatus for selecting one of a plurality of bus interface configurations to use
Provided are a method and apparatus for selecting one of a plurality of bus interface configurations to use. Selection is made of a first bus interface...
US-1,018,5567 Multilevel conversion table cache for translating guest instructions to native instructions
A method for translating instructions for a processor. The method includes accessing a guest instruction and performing a first level translation of the guest...
US-1,018,5566 Migrating tasks between asymmetric computing elements of a multi-core processor
In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core...
US-1,018,5562 Conflict mask generation
Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can...
US-1,018,5547 Techniques for distributed operation of secure controllers
Various embodiments are generally directed to techniques for supporting the distributed execution of a task routine among multiple secure controllers...
US-1,018,5511 Technologies for managing an operational characteristic of a solid state drive
Technologies for managing an operational characteristic of a solid state drive include monitoring the operational characteristic to determine whether the...
US-1,018,5501 Method and apparatus for pinning memory pages in a multi-level system memory
An apparatus is described. The apparatus includes a memory controller to interface with a multi-level system memory. The memory controller includes a pinning...
US-1,018,5401 Determination of cursor position on remote display screen based on bluetooth angle of arrival
Systems, apparatuses and methods may determine the exact position of a cursor on the screen of a display device when the user is located at a predetermined...
US-1,018,5385 Method and apparatus to reduce idle link power in a platform
A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform...
US-1,018,5382 Multiple voltage identification (VID) power architecture, a digital synthesizable low dropout regulator, and...
Described is an apparatus comprising: first and second processing cores; and a PCU which is operable to: generate a first VID for an off-die regulator external...
US-1,018,5349 Apparatus and method for extending frequency range of a circuit and for over-clocking or under-clocking
Described is an apparatus for over-clocking or under-clocking, the apparatus comprises: a locked loop (e.g., phase locked loop or frequency locked loop) having...
US-1,018,4983 Interface independent test boot method and apparatus using automatic test equipment
Computer device(s), apparatus(es), and methods enable and/or perform interface independent test boot of a System on Chip (SoC). A test Direct Memory Access...
US-1,018,4977 Devices and methods for testing integrated circuits
An integrated circuit includes a first power unit, a second power unit, and a selection switch. The first power unit generates a first output voltage and is...
US-1,018,4961 Current balancing, current sensor, and phase balancing apparatus and method for a voltage regulator
Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with...
US-1,018,2446 Apparatus, system and method of selecting a wireless communication channel
Some demonstrative embodiments include apparatuses, systems and/or methods of selecting a wireless communication channel to communicate in a wireless...
US-1,018,2437 Apparatus, system and method of indicating a time offset using a grant frame
Some demonstrative embodiments include apparatuses, devices, systems and methods of dynamic allocation using a grant frame. For example, a wireless station may...
US-1,018,2398 Downstream device service latency reporting for power management
An apparatus is provided that includes a processor, a memory controller coupled to the processor to provide access to a system memory, and an interface...
US-1,018,2369 Flow control with acknowledgment feedback
Computer readable media, methods, and apparatuses for flow control with acknowledgment feedback. An apparatus of a wireless device comprising: memory; and...
US-1,018,2362 Mechanisms of virtual clear channel assessment for Wi-Fi devices
Described are methods and devices for increasing the efficiency of Wi-Fi networks by increased spatial reuse, which refers to sharing the same wireless spectral...
US-1,018,2245 Content adaptive quality restoration filtering for next generation video coding
Techniques related to quality restoration filtering for video coding are described.
US-1,018,2217 Projection device and a method of manufacturing a projection device
The present disclosure provides a projection device and manufacturing method, comprising the steps of fixing the positions of a red light source, green light...
US-1,018,2181 Synchronization of rolling shutter camera and dynamic flash light
Various embodiments may be generally directed to techniques for synchronizing operation of a flash light with operation of a camera using a rolling shutter for...
US-1,018,1996 Trigger frame recovery
Methods, computer readable media, and wireless apparatuses are disclosed for trigger frame recovery. An apparatus of a wireless device is disclosed. The...
US-1,018,1975 Override subsystems for rapid recovery from serial-link errors
An override subsystem on the host side of a serial data link between the host and a peripheral detects and diagnoses link errors by comparing the states of the...
US-1,018,1969 High performance receiver with single calibration voltage
An apparatus is described that includes a receiver. The receive includes a data sampler, a positive error sampler and a negative error sampler each having...
US-1,018,1946 Cryptographic protection of I/O data for DMA capable I/O controllers
Technologies for cryptographic protection of I/O data include a computing device with one or more I/O controllers. Each I/O controller may generate a direct...
US-1,018,1945 Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes...
US-1,018,1940 Apparatuses and methods for reducing switching jitter
Described are apparatuses and methods for reducing channel physical layer (C-PHY) switching jitter. An apparatus may include a pattern dependent delay circuit...
US-1,018,1886 Apparatus, system and method of beamforming training
Some demonstrative embodiments include devices, systems and/or methods of wireless communication via multiple antenna assemblies. For example, a device may...
US-1,018,1856 Digital phase locked loop frequency estimation
A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a Voltage Controlled Oscillator...
US-1,018,1682 Ungrounded shield for an electrical connector
Particular embodiments described herein provide for a connector shield that can include a main body, a shield portion to shield electromagnetic radiation from a...
US-1,018,1518 Selective epitaxially grown III-V materials based devices
A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V...
US-1,018,1456 Multi-package integrated circuit assembly with package on package interconnects
A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first...
US-1,018,1432 Computing system with a thermal interface comprising magnetic particles
Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some...
US-1,018,1329 Audio processing circuit and method for reducing noise in an audio signal
An audio processing device includes a first microphone configured to receive a first signal a second microphone configured to receive a second signal, a noise...
US-1,018,1171 Sharing resources between a CPU and GPU
A technique to share execution resources. In one embodiment, a CPU and a GPU share resources according to workload, power considerations, or available resources...
US-1,018,1117 Methods and arrangements for a personal point of sale device
Logic to register a personal point of sale (POS) device. Logic may communicate with the registration processor to establish a secure communication channel....
US-1,018,1073 Technologies for efficient identity recognition based on skin features
Technologies for efficient identity recognition based on skin features include a compute device. The compute device includes an image capture device and an...
US-1,018,1052 Notification of contact status of remote user
Technologies for informing a remote user of a local user's availability to receive a contact on a communication device are disclosed. The availability of the...
US-1,018,1027 Interface between a device and a secure processing environment
Embodiments of an invention for an interface between a device and a secure processing environment are disclosed. In one embodiment, a system includes a...
US-1,018,1001 Methods and apparatus for automatically implementing a compensating reset for retimed circuitry
A compensating initialization module may be automatically inserted into a design to compensate for register retiming which changes the designs behavior under...
US-1,018,0928 Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero...
Heterogeneous hardware accelerator architectures for processing sparse matrix data having skewed non-zero distributions are described. An accelerator includes...
US-1,018,0927 Device, system and method for communication with heterogeneous physical layers
A device to process data packets for communication across PHY layers which are of different respective communication protocols. In an embodiment, the device...
US-1,018,0911 Synchronizing a translation lookaside buffer with an extended paging table
A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest...
US-1,018,0903 Hybrid hardware and software implementation of transactional memory access
Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a...
US-1,018,0856 Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
A method for performing dynamic port remapping during instruction scheduling in an out of order microprocessor is disclosed. The method comprises selecting and...
US-1,018,0854 Processor extensions to identify and avoid tracking conflicts between virtual machine monitor and guest virtual...
A processing system includes an execution unit, communicatively coupled to an architecturally-protected memory, the execution unit comprising a logic circuit to...
US-1,018,0838 Multi-register gather instruction
A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand...
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