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Patent # Description
US-1,019,3683 Methods and devices for self-interference cancelation
A communication circuit arrangement includes a signal path circuit configured to separately apply a kernel dimension filter and a delay tap dimension filter to...
US-1,019,3664 Enhanced retry count for uplink multi-user transmission
This disclosure describes systems, methods, and devices related to enhanced retry count for an uplink (UL) multi-user (MU) transmission. A device may identify a...
US-1,019,3613 Ping pong beamforming
Embodiments of the present disclosure provide an iterative procedure relying on ping-pong transmissions between two antenna arrays to determine desired...
US-1,019,3591 Methods and devices for controlling receive configurations in wireless communications
Methods and devices including a first receiver configured to demodulate a first down-converted signal; a second receiver configured to demodulate a second...
US-1,019,3548 Biasing scheme for high voltage circuits using low voltage devices
Some embodiments include apparatus and methods having a first node to receive a supply voltage, a second node to receive a first bias voltage, a third node to...
US-1,019,3536 Shared keeper and footer flip-flop
An apparatus is provided which comprises: a clock node; a first inverter having an input coupled to the clock node; a data node; a master latch with a shared...
US-1,019,3493 Multi-surface solar cell packaging for self-powered electronic devices
A solar cell assembly includes a bendable substrate and multiple solar cells to be mounted over different surfaces of an electronic device. The bendable...
US-1,019,3374 Multifunction battery charging and haptic device
Techniques for implementing a multifunction device with battery charging and haptic feedback capabilities are described. An example of an electronic device...
US-1,019,3308 Semiconductor laser with tensile strained InAlAs electron blocker for 1310 nanometer high temperature operation
Embodiments may relate to a multiple quantum well (MQW) laser for operating at high temperatures, comprising at least one quantum well made of compressively...
US-1,019,3304 Failsafe pulsed laser driver
A failsafe pulsed laser driver and method for using the same are disclosed. In one embodiment, an apparatus comprises a laser array having a plurality of...
US-1,019,3288 Snap button fastener providing electrical connection
Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the...
US-1,019,3018 Compact low power head-mounted display with light emitting diodes that exhibit a desired beam angle
A display panel is described which includes Light Emitting Diodes (LEDs) that exhibit a specified beam angle. The display panel can be used for a head-mounted...
US-1,019,2969 Transistor gate metal with laterally graduated work function
Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and...
US-1,019,2840 Ball pad with a plurality of lobes
In some forms, an electronic assembly includes a substrate; and a ball pad mounted on the substrate, wherein the ball pad includes a plurality of lobes...
US-1,019,2810 Underfill material flow control for reduced die-to-die spacing in semiconductor packages
Underfill material flow control for reduced die-to-die spacing in semiconductor packages and the resulting semiconductor packages are described. In an example,...
US-1,019,2633 Low cost inbuilt deterministic tester for SOC testing
A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as...
US-1,019,2351 Anti-aliasing adaptive shader with pixel tile coverage raster rule system, apparatus and method
Systems, apparatuses and methods may provide away to render edges of an object defined by multiple tessellation triangles. More particularly, systems,...
US-1,019,2313 Networked capture and 3D display of localized, segmented images
Systems, devices and methods are described including receiving a source image having a foreground portion and a background portion, where the background portion...
US-1,019,2281 Graphics command parsing mechanism
A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill...
US-1,019,2054 Automatic pairing of IO devices with hardware secure elements
Methods and systems may provide for receiving at a secure element of a system, during a boot process of the system, a first pairing authentication value from a...
US-1,019,1877 Architecture for software defined interconnect switch
An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and...
US-1,019,1834 Methods and systems to identify and reproduce concurrency violations in multi-threaded programs
Methods and systems to identify and reproduce concurrency violations in multi-threaded programs are disclosed. An example method disclosed herein comprises...
US-1,019,1784 Adaptive queued locking for control of speculative execution
Adaptive queued locking for control of speculative execution is disclosed. An example apparatus includes a queue controller to control removal of threads from a...
US-1,019,1759 Apparatus and method for scheduling graphics processing unit workloads from virtual machines
In an embodiment, a system includes a graphics processing unit (GPU) that includes one or more GPU engines, and a microcontroller. The microcontroller is to...
US-1,019,1749 Scatter reduction instruction
Single Instruction, Multiple Data (SIMD) technologies are described. A processing device can include a processor core and a memory. The processor core can...
US-1,019,1748 Instruction and logic for in-order handling in an out-of-order processor
In one embodiment, a processor includes a decode logic, an issue logic to issue decoded instructions, and at least one execution logic to execute issued...
US-1,019,1746 Accelerated code optimizer for a multiengine microprocessor
A method for accelerating code optimization a microprocessor. The method includes fetching an incoming microinstruction sequence using an instruction fetch...
US-1,019,1745 Optimized call-return and binary translation
In one example a processor includes a region formation engine to identify a region of code for translation from a guest instruction set architecture to a native...
US-1,019,1744 Apparatuses, methods, and systems for element sorting of vectors
Systems, methods, and apparatuses relating to element sorting of vectors are described. In one embodiment, a processor includes a decoder to decode an...
US-1,019,1743 Versatile packed data comparison processors, methods, systems, and instructions
A processor including a decode unit to decode a versatile packed data compare instruction to indicate a first source packed data operand to include a first...
US-1,019,1742 Mechanism for saving and retrieving micro-architecture context
A processor saves micro-architectural contexts to increase the efficiency of code execution and power management. Power management hardware during runtime...
US-1,019,1740 Deinterleave strided data elements processors, methods, systems, and instructions
A method performed by a processor includes receiving an instruction. The instruction indicating a source operand, indicating a stride, indicating at least one...
US-1,019,1724 Compiler-based instruction scoreboarding
Methods and apparatus relating to techniques for compiler-based instruction scoreboarding. In an example, an apparatus comprises logic, at least partially...
US-1,019,1689 Systems and methods for page management using local page information
Systems for page management using local page information are disclosed. The system may include a processor, including a memory controller, and a memory,...
US-1,019,1684 Technologies for flexibly compressing and decompressing data
Technologies for flexibly compressing data include a computing device having an accelerator complex that is to receive a compression job request and schedule...
US-1,019,1539 User aware odometry correction technology
Systems, apparatuses and methods may provide for technology to detect a pose drift condition with respect to a head mounted display based on one or more first...
US-1,019,1532 Configuring power management functionality in a processor
In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor...
US-1,019,1376 Cross scan proximity correction with ebeam universal cutter
Lithographic apparatuses suitable for, and methodologies involving, complementary e-beam lithography (CEBL) are described. In an example, a column for an e-beam...
US-1,019,0922 Method and apparatus for calibrating a sensor
Described is a current-mode thermal sensor with calibration apparatus which comprises: a first transistor with a gate terminal coupled to a first node; a second...
US-1,019,0894 Technologies for controlling degradation of sensing circuits
Technologies for controlling degradation of a sensor mote including detecting a trigger event and initiating degradation of at least a portion of the sensor...
US-1,018,8931 Smart baseball first base or home plate
Briefly, in accordance with one or more embodiments, a smart base for a baseball system or a softball system comprises a sensor to detect a first time at which...
US-D839,108 Portable electronic measurement device
US-1,018,7998 Zero-misalignment via-pad structures
A photoresist is deposited on a seed layer on a substrate. A first region of the photoresist is removed to expose a first portion of the seed layer to form a...
US-1,018,7996 Printed circuit board with a recess to accommodate discrete components in a package
Embodiments of the present disclosure provide techniques for a printed circuit board (PCB) with a recess to accommodate discrete components of a package...
US-1,018,7982 Circuit board structures for thermal insulation and method of making same
Techniques and mechanisms for providing thermal insulation with a circuit board. In an embodiment, a circuit board comprises a metal core and an electrical...
US-1,018,7889 Classification of basic service sets based on transmission opportunity holder addresses
Methods, apparatuses, and computer-readable media for classification of basic service sets (BSS) based on transmission opportunity holder addresses are...
US-1,018,7854 Awake window protection
This disclosure describes systems, methods, and devices related to awake window (AW) protection. A device may identify a beacon frame received from a first...
US-1,018,7804 Allocating wireless channels
An apparatus and a method for allocating wireless channels are disclosed. For example, the method, by an aggregator, aggregates sensed information received from...
US-1,018,7779 Dynamically associated neighbor awareness networking (NAN) discovery windows for fine timing measurement
Certain embodiments herein relate to a dynamic pre-association between Neighbor Awareness Networking (NAN) discovery windows and fine timing measurement (FTM)...
US-1,018,7389 Technologies for supporting multiple digital rights management protocols on a client device
Technologies for supporting and implementing multiple digital rights management protocols on a client device are described. In some embodiments, the...
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