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Patent # Description
US-9,748,252 Antifuse element utilizing non-planar topology
Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements...
US-9,748,199 Thermal compression bonding process cooling manifold
Embodiments of a thermal compression bonding (TCB) process cooling manifold, a TCB process system, and a method for TCB using the cooling manifold are...
US-9,748,180 Through-body via liner deposition
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an...
US-9,748,177 Embedded structures for package-on-package architecture
Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer...
US-9,747,978 Reference architecture in a cross-point memory
The present disclosure relates to reference and sense architecture in a cross-point memory. An apparatus may include a memory controller configured to select a...
US-9,747,977 Methods and systems for verifying cell programming in phase change memory
Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase...
US-9,747,971 Row hammer refresh command
A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed...
US-9,747,967 Magnetic field-assisted memory operation
In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray...
US-9,747,781 Shoe-based wearable interaction system
A system and method of initiating a command in a computing system having a processor. A pair of wearable items are detected as being in close proximity and a...
US-9,747,717 Iterative closest point technique based on a solution of inverse kinematics problem
Techniques related to non-rigid transformations for articulated bodies are discussed. Such techniques may include repeatedly selecting target positions for...
US-9,747,657 Reducing power for 3D workloads
Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by...
US-9,747,442 Preventing malicious instruction execution
Systems and techniques for preventing malicious instruction execution are described herein. A first instance of an instruction for a graphics processing unit...
US-9,747,399 Method and apparatus for providing rule patterns on grids
Described is a machine-readable storage media having one or more machine executable instructions stored there on that when executed cause one or more processors...
US-9,747,308 Method and apparatus for searching an image, and computer-readable recording medium for executing the method
The present disclosure relates to a method and apparatus for searching an image, and to a computer-readable recording medium for executing the method. The...
US-9,747,245 Method, apparatus and system for integrating devices in a root complex
In an embodiment, an apparatus comprises: a semiconductor die including but not limited to: at least one core to execute instructions; an agent to perform at...
US-9,747,221 Dynamic pinning of virtual pages shared between different type processors of a heterogeneous computing platform
A computer system may support one or more techniques to allow dynamic pinning of the memory pages accessed by a non-CPU device, such as a graphics processing...
US-9,747,208 Instruction and logic for flush-on-fail operation
A processor includes a memory management unit and a front end including a decoder. The decoder includes logic to receive a flush-on-commit (FoC) instruction to...
US-9,747,134 RDMA (remote direct memory access) data transfer in a virtual environment
In an embodiment, a method is provided. In an embodiment, the method provides determining that a message has been placed in a send buffer; and transferring the...
US-9,747,123 Technologies for multi-level virtualization
Technologies for multi-level virtualization include a computing device having a processor that supports a root virtualization mode and a non-root virtualization...
US-9,747,118 Guest-specific microcode
Embodiments of apparatuses, methods, and systems for modifying the behavior of a guest installed to run within a VM are disclosed. In one embodiment, an...
US-9,747,108 User-level fork and join processors, methods, systems, and instructions
A processor of an aspect includes a plurality of processor elements, and a first processor element. The first processor element may perform a user-level fork...
US-9,747,105 Method and apparatus for performing a shift and exclusive or operation in a single instruction
Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In...
US-9,747,102 Memory management in secure enclaves
Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution...
US-9,747,101 Gather-op instruction to duplicate a mask and perform an operation on vector elements gathered via tracked...
Instructions and logic provide vector scatter-op and/or gather-op functionality. In some embodiments, responsive to an instruction specifying: a gather and a...
US-9,747,094 Component update using management engine
Embodiments of systems and methods for applying a component update using a management engine are disclosed. A computing device may include a management engine...
US-9,747,041 Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a...
Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having...
US-9,746,990 Selectively augmenting communications transmitted by a communication device
Technologies for selectively augmenting communications transmitted by a communication device include a communication device configured to acquire new user...
US-9,746,970 Touch-sensitive interface and method using orthogonal signaling
A touch screen system includes a capacitive touch screen (1) including a plurality of row conductors (7-1, 2 . . . n) and a column conductor (5-1). A plurality...
US-9,746,941 Sensors-based automatic reconfiguration of multiple screens in wearable devices and flexible displays
Embodiments for providing a wearable device are generally described herein. A wearable device may include a processor having memory and communicatively coupled...
US-9,746,926 Techniques for gesture-based initiation of inter-device wireless connections
Techniques for gesture-based device connections are described. For example, a method may comprise receiving video data corresponding to motion of a first...
US-9,746,910 Supporting runtime D3 and buffer flush and fill for a peripheral component interconnect device
Particular embodiments described herein provide for an apparatus that includes a means for determining a power state for a device connected to a system, a means...
US-9,746,903 Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling...
Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first...
US-9,746,899 At least one message to announce entry into relatively lower power state
An embodiment may include circuitry that may be capable of performing operations that may include generating, at least in part, at least one message to announce...
US-9,746,689 Magnetic fluid optical image stabilization
Techniques related to a method, apparatus, and systems for magnetic fluid shutter operation are described herein. For example, an apparatus may include a...
US-9,746,428 Inline inspection of the contact between conductive traces and substrate for hidden defects using white light...
Embodiments include devices, systems and processes for using a white light interferometer (WLI) microscope with a tilted objective lens to perform in-line...
US-9,746,383 Throttling memory in response to an internal temperature of a memory device
Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one...
US-9,746,001 Volumetric resistance blower apparatus and system
Some embodiments of an apparatus and system are described for a volumetric resistance blower. An apparatus may comprise a motor, a rotor comprising a...
US-9,745,628 Polymer co-location in surface-attached biopolymers and arrays of biopolymers
Embodiments of the present invention provide substrates having controllably co-located polymers of different sequences. Methods are provided that allow the...
US-9,743,558 Automatic height compensating and co-planar leveling heat removal assembly for multi-chip packages
Embodiments of the present disclosure may include a heat removal assembly that is to thermally couple with two or more dice of an electronic device. The heat...
US-9,741,832 Tunneling field effect transistors with a variable bandgap channel
Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the...
US-9,741,809 Nonplanar device with thinned lower body portion and method of fabrication
A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a...
US-9,741,734 Memory devices and systems having reduced bit line to drain select gate shorting and associated methods
3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
US-9,741,721 Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)
Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors...
US-9,741,692 Methods to form high density through-mold interconnections
Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads...
US-9,741,686 Electronic package and method of connecting a first die to a second die to form an electronic package
Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is...
US-9,741,664 High density substrate interconnect formed through inkjet printing
Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a...
US-9,741,651 Redistribution layer lines
Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a...
US-9,741,645 Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures...
Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method...
US-9,741,606 Desmear with metalized protective film
Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate...
US-9,741,405 Digital phase controlled delay circuit
An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from...
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