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Beamforming using base and differential codebooks
Embodiments of methods and apparatus for determining and/or quantizing a beamforming matrix are disclosed. In some embodiments, the determining and/or...
Removal of modulated tonal interference
In some embodiments a phase between a periodic spreading signal and an effective spreading signal modulating an interfering harmonic is determined, an amplitude...
Hybrid I/Q and polar transmitter
A hybrid polar I-Q transmitter includes an I-Q derivation circuit configured to receive a first and second I-Q data components comprising a first I-Q data pair,...
Decoder and method for decoding an encoded sequence of bits
A decoder including an input, a branch metric unit, a path metric unit, a starting state unit, and a tail path forcing unit, or alternatively, a state...
Supporting data compression using match scoring
In one embodiment, a processing system is provided. The processing system includes a memory for storing an input bit stream and a processing logic coupled to...
Partitioned data compression using accelerator
In an embodiment, a processor includes a compression accelerator coupled to a plurality of hardware processing cores. The compression accelerator is to: receive...
Package structures including discrete antennas assembled on a device
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include...
Barrier film techniques and configurations for phase-change memory
Embodiments of the present disclosure describe barrier film techniques and configurations for phase-change memory elements. In an embodiment, an apparatus...
Two-dimensional condensation for uniaxially strained semiconductor fins
Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based...
Non-planar transistors and methods of fabrication thereof
The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar...
Floating body memory cell having gates favoring different conductivity
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
Methods of forming serpentine thermal interface material and structures
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal...
Space and cost efficient incorporation of specialized input-output pins on
integrated circuit substrates
In some embodiments an Integrated Circuit package includes a plurality of system functional pins, at least one system functional pin depopulation zone, and at...
Integrated circuits with selective gate electrode recess
Integrated circuits including MOSFETs with selectively recessed gate electrodes. Transistors having recessed gate electrodes with reduced capacitive coupling...
Non-lithographically patterned directed self assembly alignment promotion
A method of an aspect includes forming a directed self assembly alignment promotion layer over a surface of a substrate having a first patterned region and a...
Inductor design with metal dummy features
Techniques are disclosed for enhancing performance of integrated or on-chip inductors by implementing a schema of conductive metal dummies in the design...
Apparatus for boosting source-line voltage to reduce leakage in resistive
Described is an apparatus comprising a leakage tracker to track leakage of a column of resistive memory cells; and a circuit for adjusting voltage on a...
Assist circuits for SRAM testing
Assist circuits for SRAM memory tests allow voltage scaling in low-power SRAMs. Word line level reduction (WLR) and negative bit line (NBL) boost assist...
Ramping inhibit voltage during memory programming
The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit...
Techniques to reduce memory cell refreshes for a memory device
Examples may include techniques to reduce memory cell refreshes for a memory device. These techniques include a control unit receiving a command to cause an...
Bad block management mechanism
A system includes a non-volatile random access memory (NVRAM) device and controller logic that detects a bad block within the device, retires the bad block and...
Resolution loss mitigation for 3D displays
Systems, devices and methods are described including determining a display type and a display mode, preparing stereoscopic image content in response to the...
Methods and arrangements for sensors
Generally, smart sensors, logic to process messages from smart sensors, and smart sensor systems are described herein. Embodiments may comprise logic such as...
Compact depth plane representation for sort last architectures
In accordance with some embodiments, a full per sample coverage mask may be used for a subset of the pixels in the tile, thereby enabling pixels that belong to...
Networked capture and 3D display of localized, segmented images
Systems, devices and methods are described including receiving a source image having a foreground portion and a background portion, where the background portion...
Determining and communicating user's emotional state related to user's
physiological and non-physiological data
According to various aspects of the present disclosure, a system and associated method and functions to determine an emotional state of a user are disclosed. In...
Image-augmented inventory management and wayfinding
Systems and methods may provide for receiving a query regarding an establishment, retrieving an output image from an image database in response to the query,...
High performance interconnect physical layer
Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane...
Inter-component communication including posted and non-posted transactions
Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a...
Apparatus and method for efficient handling of critical chunks
An apparatus and method for efficient handling of critical chunks. For example, one embodiment of an apparatus comprises a plurality of agents to perform a...
Method and apparatus for optimizing the usage of cache memories
A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one...
Selective prefetching for a sectored cache
A memory subsystem includes memory hierarchy that performs selective prefetching based on prefetch hints. A lower level memory detects a cache miss for a...
Region based technique for accurately predicting memory accesses
In one embodiment, the present invention includes a processor comprising a page tracker buffer (PTB), the PTB including a plurality of entries to store an...
Inclusive and non-inclusive tracking of local cache lines to avoid near
memory reads on cache line memory...
A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry...
Dynamically compensating for degradation of a non-volatile memory device
Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic...
Instruction for performing an overload check
A processor is described having a functional unit within an instruction execution pipeline. The functional unit having circuitry to determine whether...
Systems and methods for managing reconfigurable processor cores
Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register...
Apparatus and method for a hybrid latency-throughput processor
An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For...
Instruction and logic to perform dynamic binary translation
A micro-architecture may provide a hardware and software co-designed dynamic binary translation. The micro-architecture may invoke a method to perform a dynamic...
Low depth combinational finite field multiplier
A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising...
Presentation of direct accessed storage under a logical drive model
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct...
Virtual general-purpose I/O controller
Technologies for virtual general purpose I/O (GPIO) include a computing device having a virtual GPIO controller driver, a virtual GPIO controller firmware...
Supporting keyboard and mouse over embedded displayport without using a
universal serial bus
A human interface sink device may be selectively enabled with at least one of an embedded keyboard, embedded mouse, touch-based keyboard, a touch-based mouse...
Mechanism for facilitating power and performance management of
non-volatile memory in computing devices
A mechanism is described for facilitating power governance of non-volatile memory devices using a power governing mechanism employed at a computing device...
Mechanism to provide workload and configuration-aware deterministic
performance for microprocessors
One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may...
Individual core voltage margining
Example embodiments of core voltage margining apparatus include a plurality of voltage offset blocks disposed on a multi-core processor with each voltage offset...
Method and apparatus for hardware-assisted secure real time clock
Embodiments of a system and method for secure clock management in a mobile device, or user equipment, are generally described herein. A timer offset may be...
Projection apparatus using telecentric optics
The present invention provides a projection system (10), preferably for a head-up display e.g. on board a vehicle, comprising a laser source (1), a diffuser (3)...
Thermal expansion compensators for controlling microelectronic package
The present description relates to the field of fabricating microelectronic packages, wherein a microelectronic device may be attached to a microelectronic...
Multi-radio controller and methods for preventing interference between
Embodiments of a multi-radio controller and methods for preventing interference between co-located transceivers are generally described herein. In some...