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Patent # Description
US-1,024,2644 Transmitting display data
In some examples, a system can include a microcontroller to initialize a counter to a predetermined value for each image component of an image data slice. The...
US-1,024,2496 Adaptive sub-patches system, apparatus and method
Systems, apparatuses and methods may provide a way to subdivide a patch generated in graphics processing pipeline into sub-patches, and generate sub-patch...
US-1,024,2494 Conditional shader for graphics
An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel...
US-1,024,2493 Method and apparatus for filtered coarse pixel shading
An apparatus and method for performing coarse pixel shading (CPS). For example, one embodiment of a method comprises: A method for coarse pixel shading (CPS)...
US-1,024,2486 Augmented reality and virtual reality feedback enhancement system, apparatus and method
Systems, apparatuses and methods may provide away to render augmented reality and virtual reality (VR/AR) environment information. More particularly, systems,...
US-1,024,2423 Compute optimizations for low precision machine learning operations
One embodiment provides an accelerator module comprising a memory stack including multiple memory dies; a graphics processing unit (GPU) coupled with the memory...
US-1,024,2422 Computing methods and apparatuses with graphics and system memory conflict check
An apparatus may include a graphics processing unit (GPU) and a hypervisor. The hypervisor may include a command parser to parse graphics memory addresses...
US-1,024,2419 Compiler optimization to reduce the control flow divergence
In one embodiment a graphics processing system comprises a graphics processor having execution logic and shared memory and a shader compiler unit to compile a...
US-1,024,2418 Reconfigurable graphics processor for performance improvement
Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or...
US-1,024,2328 Tracking telecommunication expenses
The present disclosure is directed to tracking telecommunication expenses. In some implementations, a method includes aggregating data associated with...
US-1,024,2294 Target object classification using three-dimensional geometric filtering
An example apparatus for classifying target objects using three-dimensional geometric filtering includes a patch receiver to receive patches with objects to be...
US-1,024,2286 Edge-based coverage mask compression
An index is assigned to each entry in the set of possible coverage masks and two functions are generated. One function translates an index to a coverage mask....
US-1,024,2252 Expression recognition tag
An apparatus for tagging content with expression recognition information is disclosed herein. The apparatus can include an input collector to receive raw...
US-1,024,2197 Methods and apparatus to use a security coprocessor for firmware protection
A data processing system (DPS) provides protection for firmware. The DPS comprises (a) a host module comprising a management engine and (b) a security module in...
US-1,024,2038 Techniques for block-based indexing
Techniques for block-based indexing are described. In one embodiment, for example, an apparatus may comprise a multicore processor element, an assignment...
US-1,024,1954 Universal serial bus type-C power delivery
In some examples, a power delivery system includes a primary power path to provide power to a computing system. The power delivery system also includes a bypass...
US-1,024,1952 Throttling integrated link
Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an...
US-1,024,1947 Hardware-based virtual machine communication
A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access...
US-1,024,1943 Memory channel that supports near memory and far memory access
A semiconductor chip comprising memory controller circuitry having interface circuitry to couple to a memory channel. The memory controller includes first logic...
US-1,024,1932 Power saving method and apparatus for first in first out (FIFO) memories
In various embodiments, apparatuses and methods are disclosed to keep a memory clock gated when the data for a current memory address is the same as the data in...
US-1,024,1921 Avoid cache lookup for cold cache
Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially...
US-1,024,1916 Sparse superline removal
Provided are an apparatus, system, and method for sparse superline removal. In response to occupancy of a replacement tracker (RT) exceeding an RT eviction...
US-1,024,1912 Apparatus and method for implementing a multi-level memory hierarchy
A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one...
US-1,024,1885 System, apparatus and method for multi-kernel performance monitoring in a field programmable gate array
In one embodiment, a field programmable gate array (FPGA) includes: programmable logic to perform at least one function for a processor coupled to the FPGA; a...
US-1,024,1844 Techniques for heat spreading in an integrated circuit
First and second circuits in an integrated circuit that generate local hot spots are activated at different times in order to reduce heat generation within each...
US-1,024,1842 Cloud container resource binding and tasking using keys
Cloud container resource binding and tasking using keys is generally described herein. An example device to bind and perform tasks using cloud-based resource...
US-1,024,1821 Interrupt generated random number generator states
The present disclosure provides RNG states. Generating the RNG states can include creating a first VM with a first RNG state and a second VM with a second RNG...
US-1,024,1801 Method and apparatus to create register windows for parallel iterations to achieve high performance in HW-SW...
An apparatus includes a register file and a binary translator to create a plurality of strands and a plurality of iteration windows, where each iteration window...
US-1,024,1795 Guest to native block address mappings and management of native code storage
A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings...
US-1,024,1794 Apparatus and methods to support counted loop exits in a multi-strand loop processor
Embodiments described herein generally relate to the field of multi-strand out-of-order loop processing, and, more specifically, to apparatus and methods to...
US-1,024,1792 Vector frequency expand instruction
A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction,...
US-1,024,1789 Method to do control speculation on loads in a high performance strand-based loop accelerator
An apparatus includes a binary translator to hoist a load instruction in a branch of a conditional statement above the conditional statement and insert a...
US-1,024,1787 Control transfer override
Embodiments of an invention for control transfer overrides are disclosed. In one embodiment, a processor includes an instruction unit to receive a control...
US-1,024,1710 Multi-level memory with direct access
Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use...
US-1,024,1707 Techniques for organizing three-dimensional array data
Various embodiments are generally directed to storing data of a three-dimensional (3D) array in a tiled manner in which adjacent rows of adjacent planes are...
US-1,024,1631 Hybrid display integratable antennas using touch sensor trace and edge discontinuity structures
A touch panel for a display may include a touch sensor with a plurality of electrode traces. A first portion of the plurality of electrode traces may form...
US-1,024,1624 Energy sensing light emitting diode display
A display that includes energy sensors within the display itself is disclosed. An Organic Light Emitting Diode (OLED) can be made to operate both as a light...
US-1,024,1583 User command determination based on a vibration pattern
Embodiments of the present disclosure provide techniques and configurations for an apparatus to determine a command to the apparatus, based on vibration...
US-1,024,1556 Autonomously controlling a buffer of a processor
In an embodiment, an apparatus includes an input/output (I/O) buffer to couple a logic unit to another device coupled via a pad, and a logic coupled to the I/O...
US-1,024,1536 Method, apparatus and system for dynamic clock frequency control on a bus
In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may...
US-1,024,1334 Near-eye display system
The present disclosure provides a near-eye display system for generating a virtual image of a display, including: a display, a first lens array comprising a...
US-1,024,1022 Characterizing a fluid sample based on response of a non-planar structure
Apparatuses, methods and storage medium associated with characterizing a fluid sample based on response of a non-planar structure are disclosed herein. In...
US-1,024,0929 Methods and systems for vertical trajectory determination and automatic jump detection
The present disclosure provides a jump detection system for inertial measurement unit (IMU) integrated with a barometric altimeter in the same device...
US-1,023,8337 In mouth wearables for environmental safety
Systems and methods may provide for identifying sensor data associated with an intraoral device and analyzing a chemical composition of an ingestible product...
US-1,023,7911 Packet data convergence protocol (PDCP) enhancements in dual-connectivity networks
In embodiments, apparatuses, methods, and storage media may be described for identifying, by a master evolved NodeB (MeNB), one or more packet data convergence...
US-1,023,7898 Arrangement for concurrent detection of signals in a receiver
An arrangement for detection of multiple signals concurrently is disclosed. The arrangement includes a demodulator component, a mixer and a detector. The...
US-1,023,7872 Techniques for group-based spatial stream assignment signaling in 60 GHz wireless networks
Techniques for group-based spatial stream assignment signaling in 60 GHz wireless networks are described. According to various such techniques, a 60 GHz-capable...
US-1,023,7855 PUCCH resource allocation with enhanced PDCCH
Embodiments of the present disclosure include methods, apparatuses, and instructions for receiving at a user equipment (UE) of a third generation partnership...
US-1,023,7847 Enhanced paging mechanism for cellular internet of things
Technology for a mobility management entity (MME) operable to facilitate paging message transmissions using a user equipment (UE) location is disclosed. The MME...
US-1,023,7846 Wireless local area network (WLAN) selection rules
In embodiments, apparatuses, methods, and storage media may be described for identifying a wireless local area network (WLAN) selection preference rule for use...
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