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Patent # Description
US-9,871,763 Method and system for dynamic application layer gateways
A method and system are disclosed for providing functionality on a network. A mobile agent moves from a first node to a target node and, at the target node,...
US-9,871,742 Cloud compute scheduling using a heuristic contention model
Technologies for contention-aware cloud compute scheduling include a number of compute nodes in a cloud computing cluster and a cloud controller. Each compute...
US-9,871,688 Frequency-selective quadrature baseband coupling cancellation
Described herein are architectures, platforms and methods for implementing cancellation of asymmetric quadrature gain imbalance due to frequency selective...
US-9,871,682 Method, apparatus and computer program for determining an interpolated complex valued sample
In a method for determining an interpolated complex valued sample, a radial component of the interpolated sample is determined using information on a radial...
US-9,871,663 Challenge response authentication for self encrypting drives
Various embodiments are directed to a system for accessing a self-encrypting drive (SED) based on a blind challenge authentication response mechanism (BCRAM)....
US-9,871,644 Wireless device, method, and computer-readable media for transmitting and receiving high-efficiency signal fields
Wireless devices, methods, and computer-readable media for transmitting and receiving high-efficiency signal fields. An access point (AP) may include circuitry...
US-9,871,568 System detection in a high frequency band radio access technology architecture
Techniques are described herein for fast and efficient discovery of small cells by user equipment ("UE") in a wireless telecommunications network. The small...
US-9,871,535 Heterogeneous compression architecture for optimized compression ratio
A processing device includes an accelerator circuit to identify a byte in a byte stream, determine whether a first byte string starting from a first byte...
US-9,871,519 On-die termination control without a dedicated pin in a multi-rank system
A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory...
US-9,871,273 Surface mount battery and portable electronic device with integrated battery cell
Systems and methods are provided for battery cells including solid electrolytes. Solid electrolyte cells may be integrated with electronic devices. For example,...
US-9,871,117 Vertical transistor devices for embedded memory and logic technologies
Vertical transistor devices are described. For example, in one embodiment, a vertical transistor device includes an epitaxial source semiconductor region...
US-9,871,106 Heterogeneous pocket for tunneling field effect transistors (TFETs)
Embodiments of the disclosure described herein comprise a tunneling field effect transistor (TFET) having a drain region, a source region having a conductivity...
US-9,871,026 Embedded memory and power management subpackage
Embodiment of the present disclosure describe integrated circuit package assemblies that allow for relatively short connections between devices such as a...
US-9,871,007 Packaged integrated circuit device with cantilever structure
Techniques and mechanisms to facilitate connection with one or more integrated circuit (IC) dies of a packaged device. In an embodiment, the packaged device...
US-9,870,824 Iterator register for structured memory
Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one...
US-9,870,801 Systems and methods for encoding multimedia content
An interactive video/multimedia application (IVM application) may specify one or more media assets for playback. The IVM application may define the rendering,...
US-9,870,752 Display dimming in response to user
In some embodiments a detector is to detect a body of a user. A controller is to determine an area of focus of the user in response to the detector, and to dim...
US-9,870,731 Wear compensation for a display
Techniques for implementing aging compensation for a display are described. An example of an electronic device includes a display comprising pixels, each pixel...
US-9,870,640 Techniques and architecture for improved vertex processing
An apparatus may include an index buffer to store an index stream having a multiplicity of index entries corresponding to vertices of a mesh and a vertex cache...
US-9,870,637 Frame removal and replacement for stop-action animation
Various systems and methods for frame removal and replacement for stop-action animation are described herein. A system for creating a stop-motion video includes...
US-9,870,605 Accelerated lens distortion correction with near-continuous warping optimization
A digital image processing technique, such as an image warping operation, is stored in a pre-computed lookup table (LUT) prior to image processing. The LUT...
US-9,870,475 Hardware configuration reporting systems
Embodiments related to hardware configuration reporting and arbitration are disclosed herein. For example, an apparatus for hardware configuration reporting may...
US-9,870,467 Apparatus and method for implementing a forked system call in a system with a protected region
In an embodiment, at least one machine-readable storage medium includes instructions that when executed enable a system to receive, at a special library of a...
US-9,870,462 Prevention of cable-swap security attack on storage devices
Generally, this disclosure provides systems, devices, methods and computer readable media for prevention of cable swap security attacks on storage devices. A...
US-9,870,380 Methods and arrangements for device profiles in wireless networks
Embodiments provide a device profile mechanism for wireless devices. Many embodiments comprise a medium access control (MAC) sublayer logic to build frames...
US-9,870,339 Hardware processors and methods for tightly-coupled heterogeneous computing
Methods and apparatuses relating to tightly-coupled heterogeneous computing are described. In one embodiment, a hardware processor includes a plurality of...
US-9,870,338 Systems, apparatuses, and methods for performing vector packed compression and repeat
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector packed compression and repeat in response to a single vector...
US-9,870,325 Common die implementation for memory devices with independent interface paths
A memory device includes at least two independent interface paths, an interface path including multiple memory banks. The memory device can selectively operate...
US-9,870,301 High-speed debug port using standard platform connectivity
A processing device comprises a debug port controller to monitor operations of the processing device to determine whether the processing device is operating in...
US-9,870,267 Virtual vector processing
Methods and apparatus to provide virtualized vector processing are disclosed. In one embodiment, a processor includes a decode unit to decode a first...
US-9,870,209 Instruction and logic for reducing data cache evictions in an out-of-order processor
A processor includes a resource scheduler, a dispatcher, and a memory execution unit. The memory execution unit includes logic to identify an executed,...
US-9,870,169 Interleaved all-level programming of non-volatile memory
Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming...
US-9,870,069 Detection of user activities by a portable device
A portable consumer device, such as a mobile phone or a tablet computer, may be configured to collect measurements data associated with at least one of movement...
US-9,870,047 Power efficient processor architecture
In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core...
US-9,870,046 Distribution of tasks among asymmetric processing elements
Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric...
US-9,870,044 Method and apparatus for a zero voltage processor sleep state
Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A...
US-9,870,012 Digitally phase locked low dropout regulator apparatus and system using ring oscillators
Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase...
US-9,869,751 Two way time of flight positioning and security using eavesdropping
Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for improved location of mobile devices using TOF...
US-9,869,714 Integrated circuit test temperature control mechanism
A thermal controller includes a thermal control interface to receive test data from an automated test equipment (ATE) system and dynamically adjust a target...
US-9,867,276 Electronic device
Electronic device and housing for such devices are described and claimed. In one example a housing comprises a first end cap dimensioned to fit within a first...
US-9,867,210 Master station and method for HEW communication using a transmission signaling structure for a HEW signal field
Embodiments of a transmission signaling structure for HEW are defined to carry packet information to configure OFDMA receivers for demodulation of a specific...
US-9,867,207 Simultaneous scheduling request transmission in dual connectivity
Briefly, in accordance with one or more embodiments, an apparatus may be configured to receive a first scheduling request transmission for a first cell group,...
US-9,867,206 Signaling extended EARFCN and E-UTRA bands in UMTS networks
Embodiments of a user equipment (UE) and Node-B to operate in a wireless communication network using extended evolved absolute radio frequency channel numbers...
US-9,867,155 Amplitude-modulation signal and phase-modulation signal delay adjustment for polar transmitter
Methods and apparatus for calibrating a polar transmitter are provided. Calibration circuitry is configured to generate an adjustment signal that communicates...
US-9,867,140 Random access techniques for fixed devices in mobile broadband networks
Briefly, in accordance with one or more embodiments, a fixed device performs a cell search to search for one or more cells on a network and determines a...
US-9,867,133 Communication device and method for performing radio communication
A communication device is provided comprising a radio frequency circuit configured to receive a first radio frequency signal and a second radio frequency...
US-9,867,082 Methods and arrangements for communications in low power wireless networks
Embodiments may comprise an orthogonal frequency division multiplexing (OFDM) system operating in the 1 GHz and lower frequency bands. In many embodiments, the...
US-9,867,078 DRX operation for UL/DL reconfiguration
In embodiments, apparatuses, methods, and storage media may be described for identifying subframes in a radio frame on which a UE may receive a Physical...
US-9,867,073 Measurement gap repetition patterns for inter-frequency offloading in heterogeneous wireless networks
An embodiment for user equipment that receives a plurality of measurement gap repetition patterns from a network. Each measurement gap repetition pattern may be...
US-9,867,056 Opportunistic signal transmission for inter-rat co-existence
Various embodiments may be generally directed to techniques for transmitting and receiving one or more reference signals opportunistically within a window over...
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