At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.
Scalable video encoding rate adaptation based on perceived quality
Multi-layered video structures are scaled over a range of perceived quality levels. An estimated Mean Opinion Score (eMOS)-based encoder control loop is...
Platform architecture for accelerated camera control algorithms
Camera control architecture and methods that distribute control responsibilities across hard real-time and soft real-time parts. The operation of digital camera...
Pose to device mapping
Embodiments may comprise logic such as hardware and/or code to map content of a device such as a mobile device, a laptop, a desktop, or a server, to a two...
Application authentication policy for a plurality of computing devices
A method, system, and computer accessible medium are disclosed for launching an application authentication policy (AAP) application on a computing device,...
Reducing authentication confidence over time based on user history
Technologies are provided in embodiments to manage an authentication confirmation score. Embodiments are configured to identify, in absolute session time, a...
Cloud based virtual mobile device
Systems and techniques for a cloud based virtual mobile device are described herein. A virtual mobile device may be initialized to correspond to a physical...
Feedback control during planned gaps in data streams
Embodiments of the present disclosure describe systems and methods for feedback control during planned gaps in data streams. Various embodiments may include...
Simultaneous transmit and receive
A simultaneous transmit and receive (STR) technology is described. The eNB is configured with a downlink centric measurement threshold and an uplink centric...
Integrated photogrammetric light communications positioning and inertial
navigation system positioning
A mobile device includes an inertial navigation system (INS) to measure inertial quantities associated with movement of the device, and estimate a kinematic...
User equipment and methods for CSI enhancements using interference
cancellation and suppression receivers
In providing feedback to an eNB in an LTE network for downlink scheduling and link adaptation, a UE issues a channel state information (CSI) report that...
Noise-shaping circuit, digital-to-time converter, analog-to-digital
converter, digital-to-analog converter...
A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback...
A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting...
Providing orientation support in receptacles
A method of receiving a plug at a receptacle is disclosed. The method may include receiving a plug at a receptacle, the receptacle including contacts disposed...
Modular design of a high power, low passive intermodulation, active
universal distributed antenna system...
A modular high power, low passive intermodulation, active, universal, distributed antenna system interface tray that includes one or more front-end RF frequency...
Variable gate width for gate all-around transistors
Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to...
Self-aligned structures and methods for asymmetric GaN transistors and
enhancement mode operation
Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain...
Heterogeneous layer device
An embodiment includes an apparatus comprising: an N layer comprising an NMOS device having a N channel, source, and drain that are all intersected by a first...
Method for interconnecting stacked semiconductor devices
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The...
Interconnect arrangement for hexagonal attachment configurations
The present description relates to the field of fabricating microelectronic devices, wherein a microelectronic device may have a hexagonal confirmation for...
Bridge interconnect with air gap in package assembly
Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package...
Techniques to mitigate bias drift for a memory device
Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is...
Destructive reads from spin transfer torque memory under read-write
Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as...
Digitally trimmable integrated resistors including resistive memory
Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions...
Object tracking in encoded video streams
Techniques are provided for tracking objects in an encoded video stream based on data directly extracted from the video stream, thus eliminating any need for...
An apparatus, system, and method are described herein. The apparatus includes an emitter and a plurality of sensors. The emitter and the sensors are...
Avatar-based video encoding
Techniques are disclosed for performing avatar-based video encoding. In some embodiments, a video recording of an individual may be encoded utilizing an avatar...
Bi-directional morphing of two-dimensional screen-space projections
Described herein are technologies that facilitate computationally low-intensity creation of additional frames in a sequence of frames created by real-time...
Exploiting frame-to-frame coherence for optimizing color buffer clear
performance in graphics processing units
A mechanism is described for dynamically optimizing color buffer clear performance in graphics processing units. A method of embodiments, as described herein,...
Independent thread saturation of graphics processing units
Techniques to saturate a graphics processing unit (GPU) with independent threads from multiple kernels are described. An apparatus may include a graphics...
Creating secure communication channels between processing elements
Two processing elements in a single platform may communicate securely to allow the platform to take advantage of the certain cryptographic functionality in one...
Technologies for verifying components
Technologies for verifying hardware components of a computing device include retrieving platform identification data of the computing device, wherein the...
Techniques and architecture for anonymizing user data
An apparatus may include an interface to receive a multiplicity of user information samples at a respective multiplicity of instances; a processor circuit, and...
Computing device boot software authentication
Various embodiments are generally directed to authenticating a chain of components of boot software of a computing device. An apparatus comprises a processor...
Mechanism for facilitating dynamic and proactive data management for
A mechanism is described for facilitating dynamic data management for computing devices according to one embodiment. A method of embodiments, as described...
Techniques for inter-component communication based on a state of a chip
Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a...
Caching and tiering for cloud storage
Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device...
Sending packets using optimized PIO write sequences without sfences
Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to...
Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A...
Non-volatile memory sector rotation
Methods and apparatus related to non-volatile memory page sector rotation are described. In one embodiment, logic rotates the order of one or more sectors by a...
Using reliability information from multiple storage units and a parity
storage unit to recover data for a...
Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed...
Shared virtual memory
Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model...
Adjustment of execution of tasks
A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job...
Fast approximate conflict detection
The present disclosure is directed to fast approximate conflict detection. A device may comprise, for example, a memory, a processor and a fast conflict...
Apparatus and method for improved lock elision techniques
An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For...
Instruction set architecture-based inter-sequencer communications with a
In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where...
Accelerated interlane vector reduction instructions
A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector...
Instruction and logic for multiplier selectors for merging math functions
A processor includes a front end with logic to identify a multiplier, multiplicand, and mathematical mode based upon an instruction. The processor also includes...
Apparatus and method of improved extract instructions
An apparatus is described that includes instruction execution circuitry to execute first, second, third, and fourth instructions, the first and second...
Composable thin computing device
This disclosure is directed to a composable thin computing device. An example device may comprise at least a device interface module, a communication module, a...
Link power savings with state retention
Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a...