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Patent # Description
US-1,030,6413 Methods for coherent antenna switching in AoD positioning scheme
Devices and methods of estimating the AoD of a STA are generally described. The STA receives comparison symbols from a first AP antenna. The comparison symbols...
US-1,030,6182 Method and system for improving video quality during call handover
A user equipment (UE) and method of improving video call quality during handover are generally described. After determining that handover has started (306), the...
US-1,030,5976 Method and apparatus for dynamically offloading execution of machine code in an application to a virtual machine
A method for managing computing includes replicating a subset of a machine state of a first computing device onto a second computing device, wherein the subset...
US-1,030,5974 Ranking system
One embodiment provides an apparatus. The apparatus includes ranker logic. The ranker logic is to rank each of a plurality of compute nodes in a data center...
US-1,030,5897 Gesture-based signature authentication
Embodiments of the invention are generally directed to systems, methods, devices, and machine-readable mediums for implementing gesture-based signature...
US-1,030,5813 Socket management with reduced latency packet processing
Generally, this disclosure provides systems, methods and computer readable media for management of sockets and device queues for reduced latency packet...
US-1,030,5805 Technologies for adaptive routing using aggregated congestion information
Technologies for adaptive routing based on aggregated congestion information include a network switch that includes a plurality of output ports. The network...
US-1,030,5802 Reliable transport of ethernet packet data with wire-speed and packet data rate match
Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric...
US-1,030,5714 Method and apparatus for frequency interleaving
The disclosure generally relates to a method and apparatus for frequency interleaving. Specifically, an embodiment of the disclosure relates to a communication...
US-1,030,5703 Methods and apparatus for continuous time linear equalizer tuning using decision feedback equalizer adaptation...
The presently-disclosed solution enables continuous time linear equalizer (CTLE) tuning without needing to perform bit error rate (BER) measurements. Because...
US-1,030,5574 Coverage extension level for coverage limited device
Generally discussed herein are systems, apparatuses, and methods that can provide a coverage enhancement to a coverage limited device. According to an example a...
US-1,030,5570 Apparatus, system and method of dual carrier modulation with first and second spatial streams
For example, a wireless station may be configured to modulate a plurality of data bit sequences into a plurality of constellation points in first and second...
US-1,030,5529 Using materials to increase structural rigidity, decrease size, improve safety, enhance thermal performance and...
Systems and methods may provide for a device including a housing, one or more electronic components positioned within the housing, and a first cured resin...
US-1,030,5508 System for compressing floating point data
A processor comprises a first memory to store data elements that are encoded according to a floating point format including a sign field, an exponent field, and...
US-1,030,5316 Wireless charging device for wearable electronic device
Systems and methods may provide for wireless charging device of an electronic device powered by a rechargeable battery. The wireless charging device may include...
US-1,030,5292 Methods, apparatus, systems and articles of manufacture to charge a battery based on an electronic device skin...
Methods, apparatus, systems, and articles of manufacture for a battery charging device are disclosed. Example battery charging devices include a temperature...
US-1,030,5207 Connector design for high density platforms
A surface mount connector includes a housing including inner surfaces surrounding a card edge region, and outer surfaces defining an exterior region. The...
US-1,030,4956 Diffused tip extension transistor
A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the...
US-1,030,4946 Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices
Vertical integration schemes and circuit elements architectures for area scaling of semiconductor devices are described. In an example, an inverter structure...
US-1,030,4940 Gate cut and fin trim isolation for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated...
US-1,030,4929 Two-dimensional condensation for uniaxially strained semiconductor fins
Techniques are disclosed for enabling multi-sided condensation of semiconductor fins. The techniques can be employed, for instance, in fabricating fin-based...
US-1,030,4814 I/O layout footprint for multiple 1LM/2LM configurations
An apparatus is described. The apparatus includes a package on package structure. The package on package structure includes an upper package and a lower...
US-1,030,4804 System on package architecture including structures on die back side
Embodiments include devices and methods, including a device including a substrate comprising a semiconductor, the substrate including a front side comprising...
US-1,030,4799 Land grid array package extension
BGA packages with a LGA package extension. First lands on a substrate are populated with solder balls, while only solder paste is dispensed on second lands that...
US-1,030,4785 Package assembly for embedded die and associated techniques and configurations
Embodiments of the present disclosure are directed towards a package assembly for embedded die and associated techniques and configurations. In one embodiment,...
US-1,030,4769 Multi-die package
Embodiments herein may relate to a package that includes a package substrate with a first die on a first side of the package substrate and a second die on a...
US-1,030,4749 Method and apparatus for improved etch stop layer or hard mask layer of a memory device
In one embodiment, an apparatus comprises an etch stop layer comprising Aluminum Oxide and one or more of Hafnium, Silicon, or Magnesium; and a channel formed...
US-1,030,4686 Electronic devices with components formed by late binding using self-assembled monolayers
Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and...
US-1,030,4681 Dual height glass for finFET doping
Dual height glass is described for doping a fin of a field effect transistor structure in an integrated circuit. In one example, a method includes applying a...
US-1,030,4556 Read and write memory scrubber
An example system that includes a processor, a memory controller, a memory, and a memory device. The memory controller coupled to the processor. The memory...
US-1,030,4510 Destructive reads from spin transfer torque memory under read-write conditions
Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as...
US-1,030,4421 Apparatus and method for remote display and content protection in a virtualized graphics processing environment
An apparatus and method are described for efficiently rendering an transmitting to a remote display. For example, one embodiment of a remote display apparatus...
US-1,030,4418 Operating system transparent system memory abandonment
An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main...
US-1,030,4235 Ray segmentation apparatus and method for direct volume rendering
An apparatus and method are described for volumetric integration. For example, one embodiment of a graphics processing apparatus comprises: single instruction...
US-1,030,4213 Near lossless compression scheme and system for processing high dynamic range (HDR) images
An apparatus for a near lossless compression scheme is described herein. The apparatus includes an image processing pipeline and a compressor. The image...
US-1,030,4154 Coordination and increased utilization of graphics processors during inference
A mechanism is described for facilitating inference coordination and processing utilization for machine learning at autonomous machines. A method of...
US-1,030,3984 Visual search and retrieval using semantic information
An apparatus for visual search and retrieval using sematic information is described herein. The apparatus includes a controller, a scoring mechanism, an...
US-1,030,3953 Person tracking and privacy and acceleration of data using autonomous machines
A mechanism is described for facilitating person tracking and data security in machine learning at autonomous machines. A method of embodiments, as described...
US-1,030,3902 Hardware assist for privilege access violation checks
Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the...
US-1,030,3900 Technologies for secure programming of a cryptographic engine for trusted I/O
Technologies for secure programming of a cryptographic engine include a computing device with a cryptographic engine and one or more I/O controllers. The...
US-1,030,3899 Secure public cloud with protected guest-verified host control
A host Virtual Machine Monitor (VMM) operates "blindly," without the host VMM having the ability to access data within a guest virtual machine (VM) or the...
US-1,030,3834 Regional design-dependent voltage control and clocking
An integrated circuit include multiple regions, wherein at least one region includes a control circuit. The control circuit receives a target voltage value to...
US-1,030,3735 Systems, apparatuses, and methods for K nearest neighbor search
Systems, apparatuses, and methods for k-nearest neighbor (KNN) searches are described. In particular, embodiments of a KNN accelerator and its uses are...
US-1,030,3620 Maintaining processor resources during architectural events
In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second...
US-1,030,3612 Power and performance-efficient cache design for a memory encryption engine
Apparatuses, systems, and methods for hardware-level data encryption having integrity and replay protection are described. An example electronic device includes...
US-1,030,3606 Dynamic home tile mapping
Technologies for migration of dynamic home tile mapping are described. A cache controller can receive coherence messages from other processor cores on the die....
US-1,030,3605 Increasing invalid to modified protocol occurrences in a computing system
An example system on a chip (SoC) includes a processor, a cache, and a main memory. The SoC can include a first memory to store data in a memory line, wherein...
US-1,030,3594 Guaranteed forward progress mechanism
An apparatus to facilitate guaranteed forward progress for graphics data is disclosed. The apparatus includes a plurality of ports to receive and transmit...
US-1,030,3571 Data recovery in memory devices
Technology for an apparatus is described. The apparatus can include a first non-volatile memory, a second non-volatile memory to have a write access time faster...
US-1,030,3525 Systems, apparatuses, and methods for data speculation execution
Systems, methods, and apparatuses for data speculation execution (DSX) are described. In some embodiments, a hardware apparatus for performing DSX comprises a...
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