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Patent # Description
US-9,746,910 Supporting runtime D3 and buffer flush and fill for a peripheral component interconnect device
Particular embodiments described herein provide for an apparatus that includes a means for determining a power state for a device connected to a system, a means...
US-9,746,903 Method, apparatus, and system for energy efficiency and energy conservation including detecting and controlling...
Some implementations provide techniques and arrangements for adjusting a rate at which operations are performed by a processor based on a comparison of a first...
US-9,746,899 At least one message to announce entry into relatively lower power state
An embodiment may include circuitry that may be capable of performing operations that may include generating, at least in part, at least one message to announce...
US-9,746,689 Magnetic fluid optical image stabilization
Techniques related to a method, apparatus, and systems for magnetic fluid shutter operation are described herein. For example, an apparatus may include a...
US-9,746,428 Inline inspection of the contact between conductive traces and substrate for hidden defects using white light...
Embodiments include devices, systems and processes for using a white light interferometer (WLI) microscope with a tilted objective lens to perform in-line...
US-9,746,383 Throttling memory in response to an internal temperature of a memory device
Systems and methods of managing memory devices provide for reduced power consumption and better thermal management through enhanced memory throttling. In one...
US-9,746,001 Volumetric resistance blower apparatus and system
Some embodiments of an apparatus and system are described for a volumetric resistance blower. An apparatus may comprise a motor, a rotor comprising a...
US-9,745,628 Polymer co-location in surface-attached biopolymers and arrays of biopolymers
Embodiments of the present invention provide substrates having controllably co-located polymers of different sequences. Methods are provided that allow the...
US-9,743,558 Automatic height compensating and co-planar leveling heat removal assembly for multi-chip packages
Embodiments of the present disclosure may include a heat removal assembly that is to thermally couple with two or more dice of an electronic device. The heat...
US-9,741,832 Tunneling field effect transistors with a variable bandgap channel
Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the...
US-9,741,809 Nonplanar device with thinned lower body portion and method of fabrication
A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a...
US-9,741,734 Memory devices and systems having reduced bit line to drain select gate shorting and associated methods
3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
US-9,741,721 Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)
Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors...
US-9,741,692 Methods to form high density through-mold interconnections
Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads...
US-9,741,686 Electronic package and method of connecting a first die to a second die to form an electronic package
Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is...
US-9,741,664 High density substrate interconnect formed through inkjet printing
Generally discussed herein are systems and apparatuses that include a dense interconnect bridge and techniques for making the same. According to an example a...
US-9,741,651 Redistribution layer lines
Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a...
US-9,741,645 Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures...
Dense interconnect with solder cap (DISC) formation with laser ablation and resulting semiconductor structures and packages are described. For example, a method...
US-9,741,606 Desmear with metalized protective film
Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate...
US-9,741,405 Digital phase controlled delay circuit
An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from...
US-9,741,154 Recording the results of visibility tests at the input geometry object granularity
According to some embodiments of the present invention, pixel throughput may be improved by performing depth tests and recording the results on the granularity...
US-9,741,125 Method and system of background-foreground segmentation for image processing
Techniques for a system, article, and method of background-foreground segmentation for image processing may include obtaining pixel data including both...
US-9,741,053 System and method for promoting media in an online distribution platform
A system and method for promoting media in an online distribution platform includes accessing one of a plurality of gaming applications provided on an online...
US-9,740,951 Technologies for object recognition for internet-of-things edge devices
Technologies for edge device object recognition include a server and one or more edge devices in communication over a network. The server maintains an object...
US-9,740,882 Sensor privacy mode
Technologies for sensor privacy on a computing device include receiving, by a sensor controller of the computing device, sensor data from a sensor of the...
US-9,740,863 Protecting a secure boot process against side channel attacks
Embodiments of an invention for protecting a secure boot process against side channel attacks are disclosed. In one embodiment, an apparatus includes...
US-9,740,774 System and method of organizing and editing metadata
In the metadata organization system a metadata classification module dynamically reads metadata organization information, such as, for example, metadata field...
US-9,740,678 Method and system of automatic speech recognition with dynamic vocabularies
A system, article, and method of automatic speech recognition with dynamic vocabularies is described herein.
US-9,740,654 Control messaging in multislot link layer flit
A link layer control message is generated and included in a flit that is to be sent over a serial data link to a device. The flits sent over the data link are...
US-9,740,646 Early identification in transactional buffered memory
A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read...
US-9,740,644 Avoiding premature enabling of nonmaskable interrupts when returning from exceptions
A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return...
US-9,740,635 Computing method and apparatus associated with context-aware management of a file cache
Computer-readable storage media, computing devices and methods associated with file cache management are discussed herein. In embodiments, a computing device...
US-9,740,623 Object liveness tracking for use in processing device cache
A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines...
US-9,740,617 Hardware apparatuses and methods to control cache line coherence
Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache...
US-9,740,612 Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an...
US-9,740,610 Polarity based data transfer function for volatile memory
Apparatus, systems, and methods to implement polarity based data transfer function on a write data unit are described. The transfer function takes into account...
US-9,740,558 On-die ECC with error counter and internal address generation
A memory subsystem enables managing error correction information. A memory device internally performs error detection for a range of memory locations, and...
US-9,740,499 Method for implementing a line speed interconnect structure
A method for line speed interconnect processing. The method includes receiving initial inputs from an input communications path, performing a pre-sorting of the...
US-9,740,493 System and method of loop vectorization by compressing indexes and data elements from iterations based on a...
Loop vectorization methods and apparatus are disclosed. An example method includes generating a first control mask for a set of iterations of a loop by...
US-9,740,492 System management mode trust establishment for OS level drivers
Various embodiments are generally directed to establishing trust in system management mode. An operating system management mode driver can invoke a system...
US-9,740,490 Instruction and logic for processing text strings
Method, apparatus, and program for performing a comparison operation. The apparatus includes execution resources to execute a first instruction. In response to...
US-9,740,489 Instruction and logic for processing text strings
Method, apparatus, and program for performing a comparison operation. The apparatus includes execution resources to execute a first instruction. In response to...
US-9,740,484 Processor-based apparatus and method for processing bit streams using bit-oriented instructions through...
An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the...
US-9,740,437 Mechanism to adapt garbage collection resource allocation in a solid state drive
Methods and apparatus related to a mechanism for quickly adapting garbage collection resource allocation for an incoming I/O (Input/Output) workload are...
US-9,740,433 Disabling a command associated with a memory device
In an embodiment, a memory device may contain device processing logic and a mode register. The mode register may a register that may specify a mode of operation...
US-9,740,419 Methods and apparatus to preserve data of a solid state drive during a power loss event
Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method...
US-9,740,397 System and method to control a touchscreen user interface
Various systems and methods for controlling a touchscreen user interface are described herein. A system to control the touchscreen user interface comprises: a...
US-9,740,299 Interaction with a computing device via movement of a portion of a user interface
Computing devices, computer-readable storage media, and methods associated with human computer interaction. In embodiments, a computing device may include a...
US-9,740,258 Hold-up energy storage and management
Power management circuitry initiates storage of backup energy in an energy storage resource. The backup energy is stored to power an electronic circuitry during...
US-9,740,226 Balancing power supply and demand
A method and apparatus to balance adapter power supply and computing device power demand. In one embodiment, power to/from battery pack(s) maybe controlled by...
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