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Patent # Description
US-9,654,281 Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes...
US-9,654,108 Apparatus and method having reduced flicker noise
One embodiment described is an apparatus that includes an active device structured in a semiconductor body. The semiconductor body may include a gate terminal...
US-9,653,786 Wearable antenna system
Smaller footprint electronic devices may be contained in a wearable housing, for example in a housing forming a portion of a watch that is worn on a user's...
US-9,653,439 Three dimensional structures within mold compound
A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the...
US-9,652,849 Techniques for rapid stereo reconstruction from images
Stereo image reconstruction techniques are described. An image from a root viewpoint is translated to an image from another viewpoint. Homography fitting is...
US-9,652,609 Entry/exit architecture for protected device modules
The entry/exit architecture may be a critical component of a protection framework using a secure enclaves-like trust framework for coprocessors. The entry/exit...
US-9,652,384 Apparatus, system and method for caching compressed data
Techniques and mechanisms to efficiently cache data based on compression of such data. The technologies of the present disclosure include cache systems,...
US-9,652,321 Recovery algorithm in non-volatile memory
Apparatus, systems, and methods for Recovery algorithm in memory are described. In one embodiment, a controller comprises logic to receive a read request from a...
US-9,652,268 Instruction and logic for support of code modification
A processor includes support for executing binary-translated code including code modifications. The processor includes a processor core that includes a cache to...
US-9,652,259 Apparatus and method for managing register information in a processing system
The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a...
US-9,652,237 Stateless capture of data linear addresses during precise event based sampling
A processor includes a logic for stateless capture of data linear addresses (DLA) during precise event based sampling (PEBS) for an out-of-order execution...
US-9,652,236 Instruction and logic for non-blocking register reclamation
A processor includes a logic to execute a first instruction and a second instruction. The first instruction is ordered before the second instruction. Each...
US-9,652,018 Adjusting power consumption of a processing element based on types of workloads to be executed
Methods and apparatus relating to multi-level CPU (Central Processing Unit) high current protection are described. In one embodiment, different workloads may be...
US-9,651,672 Systems and methods for time synchronization
A method and system for time synchronization in a mobile device are disclosed. The method includes negotiating a synchronization schedule. The synchronization...
US-9,651,610 Visible laser probing for circuit debug and defect analysis
Visible laser probing is described. In one example a probe device has a laser configured to provide a laser beam at a visible wavelength, an objective lens...
US-9,648,733 Method of forming a substrate core structure using microvia laser drilling and conductive layer pre-patterning...
A method of fabricating a substrate core structure comprises: providing first and second patterned conductive layers defining openings therein on each side of a...
US-9,648,602 Fast switching of forward link in wireless system
A technique for distributing channel allocation information in a demand access communication system. Multiple access codes are used that have a defined code...
US-9,648,589 Multiple radio devices for implementing dynamic band access background
A system and method are provided to implement dynamic spectrum access with individual multi-mode devices that incorporate multiple radios in a single device. A...
US-9,648,582 RAN paging mechanism to enable enhanced coverage mode
Devices and methods of enhanced coverage (EC) paging are generally described. An evolved Node-B (eNB) may transmit multiple EC paging messages to user equipment...
US-9,648,555 Techniques for wireless network discovery and selection support
Techniques for wireless network discovery and selection support are described. In one embodiment, for example, an evolved packet core (EPC) node may comprise a...
US-9,648,476 Methods and arrangements for sensors
Generally, smart sensors, logic to process messages from smart sensors, and smart sensor systems are described herein. Embodiments may comprise logic such as...
US-9,648,457 Multi-signal geometric location sensing for access control
Various embodiments are generally directed to the provision and use of geometric location based security systems that use multiple beacons for determining a...
US-9,648,338 Video codec and motion estimation method
The invention provides a video codec. In one embodiment, the video codec is coupled to an outer memory storing a reference frame, and comprises an interface...
US-9,647,863 Techniques to manage dwell times for pilot rotation
Techniques to manage dwell times for pilot rotation are described. An apparatus may comprise a memory configured to store a data structure with a set of...
US-9,647,831 Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a "one round" pass for aes...
US-9,647,818 Apparatus and method for single-tone device discovery in wireless communication networks
Embodiments of wireless communication devices and methods for device discovery is generally described herein. Some of these embodiments describe an apparatus...
US-9,647,804 Multi-carrier configuration, activation and scheduling
Embodiments of block acknowledgements request apparatus, systems, and methods are generally described herein. Other embodiments may be described and claimed. An...
US-9,647,735 Hybrid digital and analog beamforming for large antenna arrays
A hybrid digital and analog beamforming device for a node operable with an antenna array is disclosed. In an example, the hybrid digital and analog beamforming...
US-9,647,678 Method for operating radio frequency digital to analog conversion circuitry in the event of a first and a...
A method for operating a radio frequency digital to analog conversion circuitry with a number of cells if a first input sample and a subsequent second input...
US-9,647,636 Piezoelectric package-integrated delay lines for radio frequency identification tags
Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of...
US-9,647,363 Techniques and configurations to control movement and position of surface mounted electrical devices
Embodiments of the present disclosure are directed towards techniques and configurations to control movement and position of surface mounted electrical devices....
US-9,647,208 Low voltage embedded memory having conductive oxide and electrode stacks
Low voltage embedded memory having conductive oxide and electrode stacks is described. For example, a material layer stack for a memory element includes a first...
US-9,646,970 Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
US-9,646,953 Integrated circuit packaging techniques and configurations for small form-factor or wearable devices
Embodiments of the present disclosure are directed toward integrated circuit (IC) packaging techniques and configurations for small form-factor or wearable...
US-9,646,952 Microelectronic package debug access ports
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,...
US-9,646,910 Integrated heat spreader that maximizes heat transfer from a multi-chip package
In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed...
US-9,646,903 Thermoset polymides for microelectronic applications
Dendrimer/hyperbranched materials are combined with polyimide to form a low CTE material for use as a dielectric substrate layer or an underfill. In the...
US-9,646,890 Replacement metal gates to enhance transistor strain
Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.
US-9,646,856 Method of manufacturing a semiconductor device including removing a relief layer from back surface of...
A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad...
US-9,646,854 Embedded circuit patterning feature selective electroless copper plating
Embodiments describe the selective electroless plating of dielectric layers. According to an embodiment, a dielectric layer is patterned to form one or more...
US-9,646,851 Embedded semiconductive chips in reconstituted wafers, and systems containing same
A reconstituted wafer includes a rigid mass with a flat surface and a base surface disposed parallel planar to the flat surface. A plurality of dice are...
US-9,646,822 Active regions with compatible dielectric layers
A method to form a semiconductor structure with an active region and a compatible dielectric layer is described. In one embodiment, a semiconductor structure...
US-9,646,720 Self-repair logic for stacked memory architecture
Self-repair logic for stacked memory architecture. An embodiment of a memory device includes a memory stack having one or more memory die elements, including a...
US-9,646,660 Selectable memory access time
The present disclosure relates to selectable memory access time. An apparatus includes a memory controller. The memory controller is configured to select a...
US-9,646,657 Power loss capacitor test using voltage ripple
These present disclosure provides techniques to determine the capacitance of a power loss capacitor based on voltage ripple. The power loss capacitor may be a...
US-9,646,630 Voice recognition via wide range adaptive beam forming and multi-channel audio data
An apparatus, system, and computer readable media for data pre-processing and processing for voice recognition are described herein. The apparatus includes...
US-9,646,570 Mechanism for facilitating improved copying of graphics data on computing devices
A mechanism is described for facilitating improved copying of graphics data at computing devices according to one embodiment. A method of embodiments, as...
US-9,646,522 Enhanced information delivery using a transparent display
Information is delivered about a particular external environment using a transparent display. In one embodiment, a method includes determining a position of a...
US-9,646,426 Methods and devices for determining a location estimate
Generally discussed herein are systems and apparatuses for managing a plurality of location providers and/or assigning a location provider to provide a location...
US-9,646,216 Multiple user biometric for authentication to secured resources
Various embodiments are generally directed to the provision and use of multiple person biometric authentication systems. An apparatus including a processor...
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