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Patent # Description
US-1,025,2659 Autonomous mobile goods transfer
Disclosed in some examples, are devices, methods, systems, and machine readable mediums that provide for automated goods exchange between autonomous vehicles...
US-1,025,1273 Mainboard assembly including a package overlying a die directly attached to the mainboard
Disclosed are embodiments of a system-level assembly including an integrated circuit (IC) die directly attached to a mainboard. An IC die directly attached to a...
US-1,025,1272 Microelectronic devices designed with ultra-high-k dielectric capacitors integrated with package substrates
Embodiments of the invention include a microelectronic device that includes a plurality of organic dielectric layers and a capacitor that is integrated with a...
US-1,025,1187 Resource allocation for D2D discovery in an LTE network
Embodiments of user equipment (UE), an enhanced node B (eNB), and methods of signaling for proximity services and device-to-device (D2D) discovery in an LTE...
US-1,025,1125 Power restriction period for high efficiency WiFi
A transmit power restriction period during which lower power transmissions may occur simultaneous with reception of other frames improves reuse of a wireless...
US-1,025,1121 Apparatus, system and method of detecting one or more active wireless communication channels
Some demonstrative embodiments include apparatuses, devices, systems and methods of determining one or more active channels. For example, an apparatus may...
US-1,025,1072 Sectorized antennas for unsynchronized multiuser multiple-input and multiple-output
This disclosure describes systems, methods, and devices related to antenna adjustment for unsynchronized MU-MIMO communication. A device may determine a first...
US-1,025,1060 Modifying access to a service based on configuration data
In one example, a system for accessing services comprises a processor to detect a change in a topology of the system and request configuration data or a...
US-1,025,1011 Augmented reality virtual reality ray tracing sensory enhancement system, apparatus and method
Systems, apparatuses and methods may provide away to render augmented reality (AR) and/or virtual reality (VR) sensory enhancements using ray tracing. More...
US-1,025,0885 System and method for intracoding video data
A video system for coding a stream of video data that includes a stream of video frames divides each video frame into a matrix of a plurality of subblocks,...
US-1,025,0580 Out-of band remote authentication
In an embodiment a single user authentication event, performed between a trusted path hardware module and a service provider via an out of band communication,...
US-1,025,0524 Technologies for increasing bandwidth in partitioned hierarchical networks
Technologies for increasing the bandwidth of partitioned hierarchical networks is disclosed. If each partition of network groups of a computer network are...
US-1,025,0436 Applying framing rules for a high speed data link
Aspects of the embodiments are directed to systems, methods, and devices for error handling of data received across a multi-Lane Link compliant with a...
US-1,025,0392 Arbitrary base value for EPID calculation
Systems and methods for using an arbitrary base value for EPID calculations are provided herein. A system to use arbitrary base values in enhanced privacy ID...
US-1,025,0355 Apparatus, system and method of multi-user wireless communication
Some demonstrative embodiments include apparatuses, devices, systems and methods of multi-user (MU) wireless communication. For example, a wireless station may...
US-1,025,0278 Compression of a set of integers
These present disclosure provides devices and techniques to compress a list of integers. A circuit may include a sorter to sort a list of integers and a...
US-1,024,9925 Dielectric waveguide bundle including a supporting feature for connecting first and second server boards
An apparatus comprises a plurality of waveguides, wherein the waveguides include a dielectric material; an outer shell; and a supporting feature within the...
US-1,024,9924 Compact via structures and method of making same
Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In...
US-1,024,9908 Systems, methods and devices for creating a Li-metal edge-wise cell
A new battery cell structure uses a battery cell structure comprising a plurality of strips so that only a fraction of the power in the cell can be fed to a...
US-1,024,9742 Offstate parasitic leakage reduction for tunneling field effect transistors
A method including forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate including a blocking material...
US-1,024,9740 Ge nano wire transistor with GaAs as the sacrificial layer
An apparatus including a three-dimensional semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region,...
US-1,024,9598 Integrated circuit package having wirebonded multi-die stack
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first...
US-1,024,9597 Systems, methods, and apparatuses for implementing die recovery in two-level memory (2LM) stacked die subsystems
Systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems are described. A stacked semiconductor package...
US-1,024,9588 Designs and methods for conductive bumps
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor...
US-1,024,9515 Electronic device package
Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the...
US-1,024,9490 Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and...
A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or...
US-1,024,9351 Memory device with flexible internal data write control circuitry
A memory subsystem is enabled with a write pattern command. The write pattern command can have a different command encoding from other write commands. The write...
US-1,024,9322 Audio processing devices and audio processing methods
An audio processing device is described comprising an energy distribution determiner configured to determine an energy distribution of a sound and an acoustical...
US-1,024,9079 Relaxed sorting in a position-only pipeline
In the cull pipe, positions of the vertices of a triangle have already been computed and these coordinates may be exploited by taking and sorting triangle...
US-1,024,9073 Distributed frame buffer and API for scalable parallel rendering
Embodiments provide for a graphics processing apparatus comprising multiple compute nodes coupled to a communication layer, a rendering system executing on the...
US-1,024,9017 Apparatus and method for shared resource partitioning through credit management
An apparatus is provided which comprises: a first engine buffer to receive a first engine request; a first engine register coupled to the first engine buffer,...
US-1,024,8906 Neuromorphic circuits for storing and generating connectivity information
A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic...
US-1,024,8839 Locating objects within depth images
In accordance with some embodiments, connected-component labeling is performed in both the screen dimensions (which may be referred to as the x and y...
US-1,024,8791 Technologies for secure hardware and software attestation for trusted I/O
Technologies for trusted I/O attestation and verification include a computing device with a cryptographic engine and one or more I/O controllers. The computing...
US-1,024,8786 Platform security using processor assists
Systems, apparatuses and methods may provide for detecting an attempt by an operating system (OS) to access a non-OS managed resource and injecting, in response...
US-1,024,8591 High performance interconnect
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be...
US-1,024,8579 Method, apparatus, and instructions for safely storing secrets in system memory
Embodiments of an invention for method, apparatus, and instructions for safely storing secrets in system memory are disclosed. In one embodiment, a processor...
US-1,024,8574 Input/output translation lookaside buffer prefetching
Embodiments of apparatuses, methods, and systems for input/output translation lookaside buffer (IOTLB) prefetching are described. In an embodiment, an apparatus...
US-1,024,8570 Methods, systems and apparatus for predicting the way of a set associative cache
A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of...
US-1,024,8568 Efficient data transfer between a processor core and an accelerator
A processor writes input data to a cache line of a shared cache, wherein the input data is ready to be operated on by an accelerator. It then notifies an...
US-1,024,8524 Instruction and logic to test transactional execution status
Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start...
US-1,024,8492 Method of executing programs in an electronic system for applications with functional safety comprising a...
A method for executing programs (P) in an electronic system for applications provided with functional safety that includes a single-processor or multiprocessor...
US-1,024,8488 Fault tolerance and detection by replication of input data and evaluating a packed data execution result
Systems, methods, and apparatuses for fault tolerance and detection are described. For example, an apparatus including circuitry to replicate input sources of...
US-1,024,8486 Memory monitor
Various systems and methods for providing a memory monitor are provided herein. An integrated circuit and memory are disposed in a computer system. The...
US-1,024,8484 Prioritized error-detection and scheduling
An integrated circuit may include a plurality of configuration random access memory (CRAM) sectors that configure logic sectors to perform user-defined...
US-1,024,8428 Securely booting a computing device
Technologies for securely booting a computing device includes a security engine of the computing device that consecutively determines a hash value for each...
US-1,024,8424 Control flow integrity
One embodiment provides an apparatus. The apparatus includes collector circuitry to capture processor trace (PT) data from a PT driver. The PT data includes a...
US-1,024,8422 Systems, apparatuses, and methods for snooping persistent memory store addresses
Systems, methods, and apparatuses for executing an instruction are described. In some embodiments, a decoder circuit decodes an instruction, wherein the...
US-1,024,8351 Set technique for phase change memory
One embodiment provides a memory controller. The memory controller includes a memory controller circuitry and a set pulse determination circuitry. The memory...
US-1,024,8343 Architectures and techniques for providing low-power storage mechanisms
Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A...
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