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Patent # Description
US-9,590,575 Amplifier stage
A differential amplifier stage may include: a first transistor having a gate terminal; a second transistor having a gate terminal; and a voltage limiting...
US-9,590,373 Providing orientation support in receptacles
A method of receiving a plug at a receptacle is disclosed. The method may include receiving a plug at a receptacle, the receptacle including contacts disposed...
US-9,590,318 Modular design of a high power, low passive intermodulation, active universal distributed antenna system...
A modular high power, low passive intermodulation, active, universal, distributed antenna system interface tray that includes one or more front-end RF frequency...
US-9,590,089 Variable gate width for gate all-around transistors
Nanowire-based gate all-around transistor devices having one or more active nanowires and one or more inactive nanowires are described herein. Methods to...
US-9,590,069 Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation
Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain...
US-9,590,051 Heterogeneous layer device
An embodiment includes an apparatus comprising: an N layer comprising an NMOS device having a N channel, source, and drain that are all intersected by a first...
US-9,589,934 Method for interconnecting stacked semiconductor devices
A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The...
US-9,589,919 Interconnect arrangement for hexagonal attachment configurations
The present description relates to the field of fabricating microelectronic devices, wherein a microelectronic device may have a hexagonal confirmation for...
US-9,589,866 Bridge interconnect with air gap in package assembly
Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package...
US-9,589,634 Techniques to mitigate bias drift for a memory device
Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is...
US-9,589,620 Destructive reads from spin transfer torque memory under read-write conditions
Systems, apparatuses and methods may provide for detecting a read-write condition in which a read operation from a location in magnetoresistive memory such as...
US-9,589,615 Digitally trimmable integrated resistors including resistive memory elements
Embodiments include a resistor, coupled on a signal path, that includes one or more resistive memory elements, such as one or more magnetic tunnel junctions...
US-9,589,363 Object tracking in encoded video streams
Techniques are provided for tracking objects in an encoded video stream based on data directly extracted from the video stream, thus eliminating any need for...
US-9,589,359 Structured stereo
An apparatus, system, and method are described herein. The apparatus includes an emitter and a plurality of sensors. The emitter and the sensors are...
US-9,589,357 Avatar-based video encoding
Techniques are disclosed for performing avatar-based video encoding. In some embodiments, a video recording of an individual may be encoded utilizing an avatar...
US-9,589,316 Bi-directional morphing of two-dimensional screen-space projections
Described herein are technologies that facilitate computationally low-intensity creation of additional frames in a sequence of frames created by real-time...
US-9,589,312 Exploiting frame-to-frame coherence for optimizing color buffer clear performance in graphics processing units
A mechanism is described for dynamically optimizing color buffer clear performance in graphics processing units. A method of embodiments, as described herein,...
US-9,589,311 Independent thread saturation of graphics processing units
Techniques to saturate a graphics processing unit (GPU) with independent threads from multiple kernels are described. An apparatus may include a graphics...
US-9,589,159 Creating secure communication channels between processing elements
Two processing elements in a single platform may communicate securely to allow the platform to take advantage of the certain cryptographic functionality in one...
US-9,589,155 Technologies for verifying components
Technologies for verifying hardware components of a computing device include retrieving platform identification data of the computing device, wherein the...
US-9,589,151 Techniques and architecture for anonymizing user data
An apparatus may include an interface to receive a multiplicity of user information samples at a respective multiplicity of instances; a processor circuit, and...
US-9,589,138 Computing device boot software authentication
Various embodiments are generally directed to authenticating a chain of components of boot software of a computing device. An apparatus comprises a processor...
US-9,589,024 Mechanism for facilitating dynamic and proactive data management for computing devices
A mechanism is described for facilitating dynamic data management for computing devices according to one embodiment. A method of embodiments, as described...
US-9,588,922 Techniques for inter-component communication based on a state of a chip select pin
Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a...
US-9,588,901 Caching and tiering for cloud storage
Various systems and methods for caching and tiering in cloud storage are described herein. A system for managing storage allocation comprises a storage device...
US-9,588,899 Sending packets using optimized PIO write sequences without sfences
Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to...
US-9,588,889 Domain state
Method and apparatus to efficiently maintain cache coherency by reading/writing a domain state field associated with a tag entry within a cache tag directory. A...
US-9,588,882 Non-volatile memory sector rotation
Methods and apparatus related to non-volatile memory page sector rotation are described. In one embodiment, logic rotates the order of one or more sectors by a...
US-9,588,841 Using reliability information from multiple storage units and a parity storage unit to recover data for a...
Provided are a method, system, and apparatus using reliability information from multiple storage units and a parity storage unit to recover data for a failed...
US-9,588,826 Shared virtual memory
Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model...
US-9,588,823 Adjustment of execution of tasks
A system and method for distributed computing, including executing a job of distributed computing on compute nodes. The speed of parallel tasks of the job...
US-9,588,814 Fast approximate conflict detection
The present disclosure is directed to fast approximate conflict detection. A device may comprise, for example, a memory, a processor and a fast conflict...
US-9,588,801 Apparatus and method for improved lock elision techniques
An apparatus and method for improving the efficiency with which speculative critical sections are executed within a transactional memory architecture. For...
US-9,588,771 Instruction set architecture-based inter-sequencer communications with a heterogeneous resource
In one embodiment, the present invention includes a method for directly communicating between an accelerator and an instruction sequencer coupled thereto, where...
US-9,588,766 Accelerated interlane vector reduction instructions
A vector reduction instruction is executed by a processor to provide efficient reduction operations on an array of data elements. The processor includes vector...
US-9,588,765 Instruction and logic for multiplier selectors for merging math functions
A processor includes a front end with logic to identify a multiplier, multiplicand, and mathematical mode based upon an instruction. The processor also includes...
US-9,588,764 Apparatus and method of improved extract instructions
An apparatus is described that includes instruction execution circuitry to execute first, second, third, and fourth instructions, the first and second...
US-9,588,581 Composable thin computing device
This disclosure is directed to a composable thin computing device. An example device may comprise at least a device interface module, a communication module, a...
US-9,588,575 Link power savings with state retention
Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a...
US-9,588,559 Configurable power supplies for dynamic current sharing
An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a...
US-9,588,356 Battery structure for eyewear apparatus
An eyewear apparatus is provided that includes a lens structure having a lens panel, and a battery structure on the lens panel. The battery structure may...
US-9,588,158 Apparatus and method for determining information on a power variation of a transmit signal
An apparatus for determining information on a power variation of a transmit signal comprises a power amplifier module, an antenna module and a power variation...
US-9,585,174 Downtilt selection in a full dimensional multiple-input multiple-output system
A technology for an enhanced node B (eNode B) in a cellular network that is operable to determine downtilt using full dimensional (FD) multiple-input...
US-9,585,168 BSS/PBSS support and schedule-free networking in 60 GHz
In accordance with various aspects of the disclosure, an apparatus is disclosed that includes a network coordinator module configured to coordinate operation in...
US-9,585,112 Systems, apparatus and methods using sync beacons in neighbor awareness networking (NAN)
Techniques are disclosed using Sync Beacons in neighbor awareness networking (NAN) in wireless networks, wherein the Sync Beacon frames use Public Action frames...
US-9,585,080 Techniques for conducting fine timing measurements
Various embodiments are generally directed to an apparatus, method and other techniques to communicate configuration information during a neighbor aware network...
US-9,585,075 Coverage boosting transmission method for LTE technology
Embodiments for boosting coverage of wireless signals are generally described herein. A wireless communication device for boosting coverage of wireless signals...
US-9,585,046 Systems, methods, and devices for social proximity fine timing measurement requests multicast signaling
Embodiments relating to systems, methods, and devices for social proximity fine timing measurement requests (FTMR) multicast signaling between mobile devices...
US-9,584,988 Communication terminal, communication device, method for processing a paging message and method for controlling...
A communication terminal is described comprising a receiver configured to receive a paging message, a detector configured to determine whether the paging...
US-9,584,950 Social network for mobile nodes
A social network may be established between mobile nodes using a wireless connection. Establishing the social network may be based on an estimated time duration...
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