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Patent # Description
US-1,020,0698 Determining chroma quantization parameters for video coding
Techniques related to determining chroma quantization parameters for video coding are discussed. Such techniques may include generating first and second chroma...
US-1,020,0668 Quality of experience reporting for combined unicast-multicast/broadcast streaming of media content
Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for monitoring and reporting quality of...
US-1,020,0515 Apparatus, system and method of controlling data flow over a communication network
Some demonstrative embodiments include apparatuses, systems and/or methods of controlling data flow over a communication network. For example, an apparatus may...
US-1,020,0514 Pre-high-efficiency (HE)-short training field preamble transmission for the HE-trigger based physical layer...
Embodiments of an access point (AP) may comprise memory and processing circuitry coupled to the memory, and transceiver circuitry coupled to the processing...
US-1,020,0472 Coordination for one-sided memory access in a partitioned global address space
Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a...
US-1,020,0410 Networked peer device round-robin security controller
A round-robin network security system implemented by a number of peer devices included in a plurality of networked peer devices. The round-robin security system...
US-1,020,0376 Computer product, method, and system to dynamically provide discovery services for host nodes of target systems...
Provided are a computer product, method, and system to dynamically provide discovery services for host nodes of target systems and storage resources in a...
US-1,020,0310 Fabric-integrated data pulling engine
In an example, there is disclosed a compute node, comprising: first one or more logic elements comprising a data producer engine to produce a datum; and a host...
US-1,020,0292 Technologies for aligning network flows to processing resources
Technologies for aligning network flows to processing resources include a computing device having multiple processing nodes, a network switch, and a network...
US-1,020,0182 Systems and methods for signaling in an increased carrier monitoring wireless communication environment
Systems and methods for signaling in an increased carrier monitoring wireless communication environment are disclosed herein. A user equipment (UE) may include...
US-1,020,0148 Smart beamwidth adaptation in wireless head-mounted displays
An apparatus and related operating method of a mmWave WHMD, are provided. The apparatus utilizes beamforming information to determine direction information...
US-1,020,0147 Sending feedback in a high efficiency service field
Apparatus, computer readable media, and methods are disclosed for sending feedback in a high efficiency service field. An apparatus is disclosed comprising...
US-1,020,0087 Wireless power receiving coil along a loop of a device
Techniques for wireless charging are described herein. For example, an apparatus includes a device formed in a loop. The apparatus may also include a receiving...
US-1,020,0046 High resolution and low power interpolator for delay chain
A delay-locked loop includes multiple inverters coupled together, wherein the inverters receive an input clock signal and output a first clock signal and a...
US-1,020,0025 Pulse-amplitude modulated hybrid comparator circuit
Some embodiments include apparatus and methods using a first latch to receive an input signal at a gate of a transistor of the first latch and compare the input...
US-1,019,9842 Power supply control system
A method and apparatus for controlling the power supply for a system. In one embodiment, a power supply apparatus comprises a rechargeable battery; and a...
US-1,019,9720 Network allocation vector operations to reduce channel access delay
Computing readable media, apparatuses, and methods for network allocation vector operations to reduce channel access delay. An apparatus of a wireless device is...
US-1,019,9354 Die sidewall interconnects for 3D chip assemblies
A stacked-chip assembly including an IC chip or die that is electrically interconnected to another chip and/or a substrate by one or more traces that are...
US-1,019,9353 Microelectronic interposer for a microelectronic package
A microelectronic interposer for a microelectronic package may be fabricated, wherein a first microelectronic device within the microelectronic package is in...
US-1,019,9346 High density substrate routing in package
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more...
US-1,019,9266 Integrated circuit interconnect structure having metal oxide adhesive layer
Integrated circuit interconnect structures having a metal oxide adhesive layer between conductive interconnects and dielectric material, as well as related...
US-1,019,9157 Stacked metal inductor
An inductor has a conductor layer formed by multiple concentric co-planar turns of ultra-thick metal (UTM) adapted to receive current at a frequency of at least...
US-1,019,9091 Retention minimum voltage determination techniques
An apparatus is described. The apparatus includes a semiconductor chip. The semiconductor chip includes a memory having multiple storage cells. The storage...
US-1,019,9084 Techniques to use chip select signals for a dual in-line memory module
Examples may include techniques to use chip select signals for a dual in-line memory module (DIMM). In some examples, the chip select signals are used with...
US-1,019,9014 Method and apparatus for managing image data for presentation on a display
An apparatus may include a memory and graphics logic operative to render a set of one or more data frames for storage in the memory using a received set of data...
US-1,019,8861 User interactive controls for a priori path navigation in virtual environment
Navigation in a virtual environment (VE) is facilitated by the creation and traversal of a 3D navigation path. A computing platform renders perspective-view...
US-1,019,8850 Method and apparatus for filtering compressed textures
An apparatus and method are described for texture compression, decompression and filtering. For example, one embodiment of a method comprises: determining...
US-1,019,8818 Complexity reduction of human interacted object recognition
In one example, a system for recognizing an object includes a processor to select from a plurality of image frames an image frame in which a view of the object...
US-1,019,8645 Preventing face-based authentication spoofing
System and techniques for preventing face-based authentication spoofing are described herein. A visible light emitter may be controlled to project a pattern...
US-1,019,8600 Transparent execution of secret content
The present application is directed to transparent execution of secret content. A device may be capable of downloading content that may include at least one...
US-1,019,8429 Automatic text language selection mechanism
A mechanism is described for facilitating automatic selection of a text language for a message according to one embodiment. A method of embodiments, as...
US-1,019,8401 Max pooling in a matrix processing architecture
In one embodiment, an apparatus comprises a multi-dimensional memory and a plurality of processing elements to perform a matrix operation, wherein the matrix...
US-1,019,8394 Reduced pin count interface
An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or...
US-1,019,8379 Early identification in transactional buffered memory
A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read...
US-1,019,8361 Memory sharing via a unified memory architecture
A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein....
US-1,019,8354 Apparatus, system, and method to flush modified data from a volatile memory to a persistent second memory
Provided are an apparatus, system, and method to flush modified data from a first memory to a persistent second memory. A first memory controller coupled to the...
US-1,019,8335 Detecting root causes of use-after-free memory errors
Methods, systems, and computer programs are presented for detecting the root cause in use-after-free (UAF) memory corruption errors. A method includes an...
US-1,019,8333 Test, validation, and debug architecture
An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test...
US-1,019,8306 Method and apparatus for a memory module to accept a command in multiple parts
Provided are a method and apparatus for a memory module to accept a command in multiple parts. A first half of a command is placed on a bus for a memory module...
US-1,019,8274 Technologies for improved hybrid sleep power management
Technologies for hybrid sleep power management include a computing device with a processor supporting a low-power idle state. In a pre-boot firmware...
US-1,019,8266 Method for populating register view data structure by using register template snapshots
A method for populating a source view data structure by using register template snapshots. The method includes receiving an incoming instruction sequence using...
US-1,019,8265 Microprocessor for gating a load operation based on entries of a prediction table
A method for gating a load operation based on entries of a prediction table is presented. The method comprises performing a look-up for the load operation in a...
US-1,019,8264 Sorting data and merging sorted data in an instruction set architecture
A processing device includes a sorting module, which adds to each of a plurality of elements a position value of a corresponding position in a register rest...
US-1,019,8248 Parallel processing of a single data buffer
Technologies for executing a serial data processing algorithm on a single variable length data buffer includes streaming segments of the buffer into a data...
US-1,019,8069 Natural human-computer interaction for virtual personal assistant systems
Technologies for natural language interactions with virtual personal assistant systems include a computing device configured to capture audio input, distort the...
US-1,019,8065 Selecting a low power state based on cache flush latency determination
In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality...
US-1,019,8060 Controlling power management in micro-server cores and peripherals
Systems and methods of enabling power management in a micro server include providing multiple cores, a power management module coupled to the cores, and one or...
US-1,019,8033 Head mounted wearable device power supply system
One embodiment provides an apparatus. The apparatus includes a source conductive path to couple to a load conductive path and to a power source. The source...
US-1,019,8027 Providing reduced latency credit information in a processor
In one embodiment, a processor includes a credit circuit to communicate credit information between a first clock domain of the processor and a second clock...
US-1,019,7737 Low back reflection echelle grating
Embodiments of the present disclosure are directed toward an optical apparatus that includes a semiconductor layer to propagate light from at least one light...
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