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Patent # Description
US-9,479,592 Remote management for a computing device
Examples are disclosed for remote management of a computing device. In some examples, a secure communication link may be established between a network...
US-9,479,506 At least one mechanism to permit, at least in part, allocation and/or configuration, at least in part, of at...
In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part,...
US-9,479,498 Providing limited access to a service device via an intermediary
Systems and methods may provide for brokering limited access to a service device via an intermediary. In one example, the method may include receiving a request...
US-9,479,392 Personal communication drone
A system of using a drone for network connectivity, the system may comprise: a connectivity module to: detect an error associated with network traffic on a...
US-9,479,364 Unequalized clock data recovery for serial I/O receiver
A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and...
US-9,479,332 Key revocation in system on chip devices
Methods and apparatus relating to key revocation in system on chip (also referred to as SOC or SoC) devices are described. In an embodiment, a storage device...
US-9,479,298 Demodulation reference signals (DMRS)for side information for interference cancellation
Embodiments for providing demodulation reference signals to provide side information for interference cancellation are generally described herein. In some...
US-9,479,246 Methods and arrangements to acknowledge fragmented frames
Logic for communications with an efficient acknowledgement (ACK) procedure for fragmented frames. Logic may determine an acknowledgement protocol to handle more...
US-9,479,233 Apparatus, system and method of multi-input-multi-output (MIMO) beamformed communication with space block coding
Some demonstrative embodiments include devices, systems and/or methods of beamformed communication with space block coding. For example, an apparatus may...
US-9,479,196 High performance interconnect link layer
Transaction data is identified and a flit is generated to include three or more slots and a floating field to be used as an extension of any one of two or more...
US-9,479,187 Predictive time-to-digital converter and method for providing a digital representation of a time interval
Predictive time-to-digital converters (TDCs) and methods for providing a digital representation of a time interval are disclosed herein. In an example, a TDC...
US-9,478,881 Snap connector for socket assembly and associated techniques and configurations
Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment,...
US-9,478,866 Orientation agnostic millimeter-wave radio link
Described herein are architectures, platforms and methods for implementing an orientation-agnostic millimeter-wave (mm-wave) antenna in a portable device.
US-9,478,734 Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same
Perpendicular spin transfer torque memory (STTM) devices with enhanced stability and methods of fabricating perpendicular STTM devices with enhanced stability...
US-9,478,643 Memory structure with self-aligned floating and control gates and associated methods
A memory structure having at least substantially aligned floating and control gates. Such a memory structure can include a control gate material disposed...
US-9,478,635 Germanium-based quantum well devices
A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close...
US-9,478,524 Multi-die semiconductor structure with intermediate vertical side chip and semiconductor package for same
Semiconductor multi-die structures having intermediate vertical side chips, and packages housing such semiconductor multi-die structures, are described. In an...
US-9,478,488 Reducing loadline impedance in a system
In one embodiment, the present invention includes a semiconductor device mounted to a first side of a circuit board; and at least one voltage regulator device...
US-9,478,476 Package for a microelectronic die, microelectronic assembly containing same, microelectronic system, and method...
A package for a microelectronic die (110) includes a first substrate (120) adjacent to a first surface (112) of the die, a second substrate (130) adjacent to...
US-9,478,308 Programmable memory device sense amplifier
Embodiments include circuits, apparatuses, and systems for programmable memory device sense amplifiers. In embodiments, an electronic circuit may include a...
US-9,478,305 Methods and apparatus to program multi-level cell memory using target-only verify
A disclosed example includes selectively precharging first bitlines of first multi-level cell (MLC) memory cells of a wordline without precharging second...
US-9,478,286 Transient current-protected threshold switching devices systems and methods
Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and...
US-9,478,273 Low resistance bitline and sourceline apparatus for improving read and write operations of a nonvolatile memory
Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each...
US-9,478,060 Techniques to provide depth-based typeface in digital documents
An apparatus may include a processor circuit and a three-dimensional (3-D) typeface module that is operative on the processor circuit to provide a choice of one...
US-9,478,037 Techniques for efficient stereo block matching for gesture recognition
Techniques to provide efficient stereo block matching may include receiving an object from a scene. Pixels in the scene may be identified based on the object....
US-9,478,000 Sharing non-page aligned memory
A method for sharing memory between a central processing unit (CPU) and an input/output (I/O) device of a computing device is described. The method may include...
US-9,477,889 Face recognition with parallel detection and tracking, and/or grouped feature motion shift tracking
Apparatuses, methods and storage medium associated with face recognition are disclosed herein. In embodiments, a method for recognizing a face may include...
US-9,477,631 Optimized credit return mechanism for packet sends
Method and apparatus for implementing an optimized credit return mechanism for packet sends. A Programmed Input/Output (PIO) send memory is partitioned into a...
US-9,477,628 Collective communications apparatus and method for parallel systems
A collective communication apparatus and method for parallel computing systems. For example, one embodiment of an apparatus comprises a plurality of processor...
US-9,477,627 Interconnect to communicate information uni-directionally
A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to...
US-9,477,622 Deterministic method to support multiple producers with multiple consumers in peer or hierarchical systems
A transaction processing method is disclosed to solve the issue of multiple producers (software and hardware) and one or more consumers operating in a peer or...
US-9,477,610 Address range priority mechanism
Method and apparatus to efficiently manage data in caches. Data in caches may be managed based on priorities assigned to the data. Data may be requested by a...
US-9,477,602 Cache refill control
A method and a device are disclosed for a cache memory refill control.
US-9,477,564 Method and apparatus for dynamic node healing in a multi-node environment
Method and apparatus for dynamic Node healing in a Multi-Node environment. A multi-node platform controller hub (MN-PCH) is configured to support multiple nodes...
US-9,477,558 Hardware supported memory logging
Logging changes to a physical memory region during a logging time interval includes: detecting a write operation to the physical memory region, wherein the...
US-9,477,533 Progress meters in parallel computing
Systems and methods may provide a set of cores capable of parallel execution of threads. Each of the cores may run code that is provided with a progress meter...
US-9,477,515 Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode
In one embodiment, the present invention includes a method for receiving control in a kernel mode via a ring transition from a user thread during execution of...
US-9,477,472 Method and apparatus for shuffling data
Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a...
US-9,477,467 Processors, methods, and systems to implement partial register accesses with masked full register accesses
A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction...
US-9,477,453 Technologies for shadow stack manipulation for binary translation systems
Technologies for shadow stack management include a computing device that, when executing a translated call routine in a translated binary, pushes a native...
US-9,477,441 Double rounded combined floating-point multiply and add
Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector...
US-9,477,409 Accelerating boot time zeroing of memory based on non-volatile memory (NVM) technology
Methods and apparatus to accelerate boot time zeroing of memory based on Non-Volatile Memory (NVM) technology are described. In an embodiment, a storage device...
US-9,477,316 Interaction with a computing device via movement of a portion of a user interface
Computing devices, computer-readable storage media, and methods associated with human computer interaction. In embodiments, a computing device may include a...
US-9,477,303 System and method for combining three-dimensional tracking with a three-dimensional display for a user interface
Systems and methods for combining three-dimensional tracking of a user's movements with a three-dimensional user interface display is described. A tracking...
US-9,477,291 Efficient integrated switching voltage regulator
Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power...
US-9,477,278 Voltage regulator
A voltage regulator may be provided that includes a first circuit to receive at least one feedback signal from a buck converter and to provide at least one...
US-9,477,275 Thermal management solution for circuit products
An apparatus including a cold plate body; a channel module disposed within the cold plate body including a channel body and a plurality of channels projecting...
US-9,477,243 System maximum current protection
A method and apparatus for providing proactive current protection. In one embodiment, the method comprises: prior to transitioning to a new state for an...
US-9,476,965 Differentiated station location
Embodiments allow a station to determine its location and report the location to a access point or other network entity. The station obtains agreement with an...
US-9,476,940 Boundary scan chain for stacked memory
A boundary scan chain for stacked memory. An embodiment of a memory device includes a system element and a memory stack including one or more memory die layers,...
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