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Patent # Description
US-1,003,3683 Sharing user information with proximate devices
Embodiments of techniques and systems for sharing user information between proximate devices are described. In embodiments, a first device may identify a...
US-1,003,3666 Techniques for virtual Ethernet switching of a multi-node fabric
Examples include techniques for virtual Ethernet switching of a multi-node fabric. In some examples, first Ethernet links coupled with a group of Ethernet...
US-1,003,3586 Technologies for autonegotiating 10G and 1G serial communications over copper cable
Technologies for autonegotiation of communications operational modes over copper cable include a network port logic having a communication link coupled to a...
US-1,003,3565 Low peak-to-average power ratio long training field sequences
This disclosure describes methods, apparatus, and systems related to a low peak-to-average power ratio (PAPR) long training field (LTF) sequences system. A...
US-1,003,3534 Methods and apparatus to provide for efficient and secure software updates
In a method for validating software updates, a data processing system contains a current version of a software component. The data processing system saves at...
US-1,003,3435 Apparatus, system and method of detecting an activity of a wireless communication device
Some demonstrative embodiments include apparatuses, systems and/or methods of detecting an activity of a wireless communication device. For example, a Near...
US-1,003,3411 Adjustable error protection for stored data
An apparatus is described that includes a semiconductor chip having memory controller logic circuitry. The memory controller logic circuitry has compression...
US-1,003,3404 Technologies for efficiently compressing data with run detection
Technologies for efficiently compressing data with run detection include a compute device. The compute device is to produce a hash as a function of a symbol at...
US-1,003,3402 Low power analog to digital converter
Described is an analog to digital converter (ADC) which comprises: a sigma-delta modulator to receive an analog signal, the sigma-delta modulator operable to...
US-1,003,3382 Method and apparatus for dynamic memory termination
Described herein are a method and an apparatus for dynamically switching between one or more finite termination impedance value settings to a memory...
US-1,003,3360 Latched comparator circuit
Some embodiments include apparatuses having input nodes to receive input signals, output nodes to provide output signals, a first stage including a first pair...
US-1,003,3230 Controlling a wireless power transmitter based on human presence
Techniques for proximity sensing in a wireless power transmitter in a system, method, and apparatus are described herein. For example, an apparatus may include...
US-1,003,3093 mmWave antennas and transmission lines on standard substrate materials
A method including disposing a transmission line or an antenna on dielectric material; and removing a portion of the dielectric material from a region adjoining...
US-1,003,2915 Non-planar transistors and methods of fabrication thereof
The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar...
US-1,003,2911 Wide band gap transistor on non-native semiconductor substrate
Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench,...
US-1,003,2857 Etchstop layers and capacitors
Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense...
US-1,003,2723 Metal layer independent version identifier
Version circuitry for use with a semiconductor chip having multiple layers includes multiple status bits. The versioning circuitry includes, for each status...
US-1,003,2707 Post-grind die backside power delivery
Disclosed is a die. The die may include a material layer, a plurality of vias, and a plurality of metal channels. The material layer may have a top side and a...
US-1,003,2643 Method and structure to contact tight pitch conductive layers with guided vias using alternating hardmasks and...
Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are...
US-1,003,2508 Method and apparatus for multi-level setback read for three dimensional crosspoint memory
In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback...
US-1,003,2507 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual...
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in...
US-1,003,2431 Mobile computing device technology and systems and methods utilizing the same
Mobile computing device technology and systems and methods using the same are described herein. In particular, mobile computing devices that may serve as a...
US-1,003,2361 Threat monitoring for crowd environments with swarm analytics
A system enables threat monitoring in a school or other "crowd" environment. The premises where the crowd environment will exist includes one or more nodes that...
US-1,003,2277 Method, apparatus, and system for displaying a graphical user interface
Technologies for displaying graphical elements on a graphical user interface include a wearable computing device to generate a captured image. The wearable...
US-1,003,2244 Method and apparatus for implementing a nearest neighbor search on a graphics processing unit (GPU)
An apparatus and method are described for implementing a nearest neighbor search on a graphics processing unit. For example, one embodiment of an apparatus...
US-1,003,2211 Anonymous electronic transactions
Techniques are disclosed for protecting privacy of parties to electronic transactions, such as transactions conducted through a GSM network. An anonymity...
US-1,003,2052 Piezoelectric package-integrated delay lines for radio frequency identification tags
Embodiments of the invention include delay line circuitry that is integrated with an organic substrate. Organic dielectric material and a plurality of...
US-1,003,1993 Application store model for dynamic reconfiguration of a field-programmable gate array (FPGA)
A computing device, computer-readable medium, and method are provided to dynamically configure an FPGA of a computing device at runtime without rebooting the...
US-1,003,1882 Sensor bus communication system
Described is an I3C Repeater. The I3C Repeater may have a first circuitry with an I3C interface, a second circuitry with an I2C interface, and a datapath...
US-1,003,1868 Dynamic bus inversion with programmable termination level to maintain programmable target ratio of ones and...
Dynamic bus inversion (DBI) for programmable levels of a ratio of ones and zeros. A transmitting device identifies a number and/or ratio of ones and zeros in a...
US-1,003,1861 Protect non-memory encryption engine (non-mee) metadata in trusted execution environment
A server, processing device and/or processor includes a processing core and a memory controller, operatively coupled to the processing core, to access data in...
US-1,003,1848 Method and apparatus for improving snooping performance in a multi-core multi-processor
A method and apparatus for improving snooping performance is disclosed. In one embodiment, one or more content addressable matches are used to determine where...
US-1,003,1847 System and method for replacement in associative memories using weighted PLRU trees
A processor includes an associative memory including ways organized in an asymmetric tree structure, a replacement control unit including a decision node...
US-1,003,1845 Method and apparatus for processing sequential writes to a block group of physical blocks in a memory device
Provided are an apparatus and method for processing sequential writes to a block group of physical blocks in a memory device. Sequential write data for a...
US-1,003,1802 Embedded ECC address mapping
Apparatus, systems, and methods to embed ECC data with cacheline data in a memory page are described. In one embodiment, an electronic device comprises a...
US-1,003,1784 Interconnect system to support the execution of instruction sequences by a plurality of partitionable engines
A global interconnect system. The global interconnect system includes a plurality of resources having data for supporting the execution of multiple code...
US-1,003,1770 System and method of delayed context switching in processor registers
Systems, articles, and methods of context switching include requesting a transition context switch deferrable until a state to be saved is smaller than at the...
US-1,003,1765 Instruction and logic for programmable fabric hierarchy and cache
A processor includes a core within a package and layers of programmable fabric within the same package as the core. The core includes logic to execute an...
US-1,003,1759 System and method for execution of a secured environment initialization instruction
A method and apparatus for initiating secure operations in a microprocessor system is described. In one embodiment, one initiating logical processor initiates...
US-1,003,1752 Distributed double-precision floating-point addition
The present embodiments relate to circuitry that efficiently performs double-precision floating-point addition operations, single-precision floating-point...
US-1,003,1699 Read voltage determination in a memory device
Technology for a system operable to write and read data from memory is described. The system can include memory and a memory controller. The memory controller...
US-1,003,1684 Techniques for a write zero operation
Examples include techniques for a write zero operation. Example techniques include forwarding a write 0 command to a memory device to cause internal activations...
US-1,003,1538 Low-power, high-performance regulator devices, systems, and associated methods
Low-power, high-performance voltage regulator circuit devices are disclosed and described. In one embodiment, such a device can include a first stage circuitry...
US-1,003,0916 Fluid flow channel for enhanced heat transfer efficiency
A heat transfer apparatus is described having a manifold. The manifold has a surface having a fluidic exit opening and a fluidic entrance opening. A fluid is to...
US-1,002,8394 Electrical interconnect formed through buildup process
This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical...
US-1,002,8322 Mechanism to enable rejection and cancellation of request actions from wireless peer-to-peer devices
Systems, apparatuses, and methods are directed to a first peer-to-peer (P2P) enabled device configured to wirelessly transmit a first request message and a...
US-1,002,8303 Clear channel assessment (CCA) in wireless networks
This disclosure describes methods, apparatus, and systems related to providing a source device more degrees of freedom in the performing CCA, and in using CCA...
US-1,002,8301 Device to-device (D2D) communications
Technology for performing device-to-device (D2D) communications is disclosed. A user equipment (UE) can identify D2D data to be transmitted from the UE. The D2D...
US-1,002,8188 Location processing in small cells implementing multiple air interfaces
A heterogeneous network which supports multiple communication technologies (e.g., communication in accordance with multiple air interface standards) in a...
US-1,002,8187 Apparatus and method for control channel monitoring in a new carrier type (NCT) wireless network
Generally, this disclosure provides apparatus and methods for improved control channel monitoring in a New Carrier Type (NCT) wireless network. A User Equipment...
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