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Method and apparatus for cloud-assisted cryptography
In an embodiment, a system includes a processor that includes private key decryption logic to decrypt an encrypted private key received from a consuming device...
Techniques associated with server transaction latency information
Examples are disclosed for determining or using server transaction latency information. In some examples, a network input/output device coupled to a server may...
Enhanced carrier sensing for multi-channel operation
In various embodiments, a multi-channel request-to-send and a multi-channel clear-to-send may be used in a wireless communications network to assure that a...
Methods and apparatus for signaling on a differential link
Methods and apparatus are disclosed for transitioning a receiver from a first state to a second state using an in-band signal over a differential serial data link.
Display driver capable of driving multiple display interfaces
A semiconductor chip is described. The semiconductor chip includes a display controller having a driver. The display controller is configurable to select a...
SMS4 acceleration hardware
Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware....
Full duplex wireless communications on devices with limited echo
Disclosed in some examples are methods, systems, and machine readable mediums which allow for wireless devices with limited echo cancellation capabilities to...
Systems and methods for data rate optimization in a WCAN system with
A method for determining an optimal pulse repetition period (PRP) in a system including a wireless transmission device operating in a static physical...
Wireless interference cancellation
Interference cancellation circuitry is provided for reconstructing a wirelessly transmitted modulated signal in a receiver using output of a decoder for...
Systems and methods for skewing DC/DC converter phases to mitigate spurs
A voltage converter system is disclosed. The system has a control unit, a multiphase converter, and a measuring unit. The control unit is configured to generate...
Battery pulse charging method and apparatus
Disclosed herein are some embodiments for safely charging a mobile system battery pack, even when the power source (e.g., adapter) voltage is at a relatively...
Extended drain non-planar MOSFETs for electrostatic discharge (ESD)
Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may...
Apparatus and method for using conductive adhesive fibers as a data
An apparatus and method for using conductive adhesive fibers as a data interface are disclosed. A particular embodiment includes: a first array of conductive...
Double-mated edge finger connector
A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a...
Non-planar quantum well device having interfacial layer and method of
Techniques are disclosed for forming a non-planar quantum well structure. In particular, the quantum well structure can be implemented with group IV or III-V...
Picture frame stiffeners for microelectronic packages
A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An...
Integrated circuit component shielding
Embodiments of shielding apparatuses are disclosed herein. In some embodiments, a shielding apparatus may include first and second conductive regions and a...
Coreless substrate with passive device pads
Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with...
AVD hardmask for damascene patterning
A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a...
Fine grained online remapping to handle memory errors
An error in a physical memory realization at a physical memory address is detected. A first physical memory line corresponding to the physical memory address is...
NAND memory addressing
Technology for performing addressing in a NAND memory is described. A defined number of address cycles supported at either a memory controller or a NAND memory...
Programming memory cells using a program pulse
Described herein are techniques related to one or more systems, apparatuses, methods, etc. for programming a memory cell through the use of a program pulse.
Multi-level cell (MLC) non-volatile memory data reading method and
Embodiments include systems, methods, and apparatuses for reading the signal-level of three-signal-level cells in a non-volatile memory (NVM). In one...
Power management in dual memory platforms
Methods, apparatuses, and systems may provide a sensor to monitor a power consumption of a non-volatile random access memory (RAM) and a volatile RAM. A switch,...
Adaptive depth offset compression
Because using the same number of bits per residual depth offset compression is not the best distribution of bits, the bits per residual may be distributed...
An importance map indicates, for each of a plurality of pixels, whether the pixel is considered important enough to be rendered. A hierarchical tree for pixels...
Blob detection in noisy images
Techniques related to blob detection in noisy images are discussed. Such techniques may include traversing a contour associated with a candidate blob contour...
Rectification techniques for heterogeneous camera arrays
Rectification techniques for camera arrays in which the resolutions, fields of view, and/or pixel sizes of various cameras may differ from one another are...
Labeling component parts of objects and detecting component properties in
Techniques related to labeling component parts and detecting component properties in imaging data are discussed. Such techniques may include generating a...
Method and apparatus for location-based recovery of stolen mobile devices
A method, apparatus, and system for locating mobile devices. The system includes a location-aware mobile device. The location-aware mobile device includes a...
Secure video ouput path
Systems and methods for secure delivery of output surface bitmaps to a display engine. An example processing system comprises: an architecturally protected...
Method and apparatus for remotely provisioning software-based security
A virtual security coprocessor is created in a first processing system. The virtual security coprocessor is then transferred to a second processing system, for...
Hardware shadow stack support for legacy guests
Technologies for shadow stack support for legacy guests include a computing device having a processor with shadow stack support. During execution of a call...
System and method for dual screen language translation
Generally, this disclosure provides systems and methods to facilitate real-time language translation between two speakers. A system may include an audio...
Memory sharing and page deduplication using indirect lines
Memory management includes maintaining a plurality of physical pages corresponding to a respective plurality of indirect lines, where each of the plurality of...
Flexible wear management for non-volatile memory
Systems and methods of memory cell wear management that can achieve a more uniform distribution of write cycles across a memory cell address space. The systems...
Techniques to perform power fail-safe caching without atomic metadata
A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a...
Testing I/O timing defects for high pin count, non-contact interfaces
Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line...
Mechanism for facilitating dynamic and efficient management of instruction
atomicity violations in software...
A mechanism is described for facilitating dynamic and efficient management of instruction atomicity violations in software programs according to one embodiment....
Minimizing performance loss on workloads that exhibit frequent core
A processor may include a cause agnostic frequency dither filter (FD filter), which may cause reduction in the frequency transitions while maintaining the...
Method and apparatus for performing a shift and exclusive or operation in
a single instruction
Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In...
Instructions and logic to vectorize conditional loops
Instructions and logic provide vectorization of conditional loops. A vector expand instruction has a parameter to specify a source vector, a parameter to...
Mechanism for interpreting touches to a pad cover over a sensor pad at a
A mechanism is described for interpreting touches to a pad cover placed over a sensor external to a computing device. A method of embodiments of the invention...
Generating audible tooltips
A processor-based system may include software which implements an audible tooltip. For example, in connection with a touch screen display, when an object is...
Techniques and apparatus for managing touch interface
An apparatus may comprise a touch-sensitive user interface, a processor circuit; and a personalized touch event filter that includes a touch trainer module for...
Dynamic core selection for heterogeneous multi-core systems
Dynamically switching cores on a heterogeneous multi-core processing system may be performed by executing program code on a first processing core. Power up of a...
Instruction and logic for store broadcast and power management
A processor includes a core with locally-gated circuitry, a decode unit, a local power gate (LPG) coupled to the locally-gated circuitry, and an execution unit....
Dynamically adjusting power of non-core processor circuitry including
In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion...
Systems and methods for implementing reduced power states
In some embodiments, provided is a way for devices to request S0ix (or the like) entry and exit.
Thermal energy storage, dissipation and EMI suppression for integrated
circuits using porous graphite sheets...
Mobile platforms and methods may provide for an integrated circuit such as a system on chip (SoC), a first heat spreader thermally coupled to the integrated...