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Patent # Description
US-9,974,002 Grouping of user terminal cell access information in a system information block
Disclosed is a method for generating and transmitting system information in a mobile radio cell. In said method, system information is grouped into several...
US-9,973,986 Systems and methods for mobility optimization in a heterogeneous network
Methods, systems, and devices for mobility optimization in a heterogeneous network are disclosed herein. A base station includes an anchor module, a context...
US-9,973,958 Systems, methods, and devices for improved inter-frequency measurement
Systems and methods for improved inter-frequency measurement are disclosed herein. User equipment (UE) may be configured to communicatively couple to an Evolved...
US-9,973,944 User equipment and methods for operation in coverage enhancement mode with physical random access channel preamble
Embodiments of a User Equipment (UE) to operate in accordance with a physical random access channel (PRACH) are disclosed herein. The UE may comprise hardware...
US-9,973,933 Spectrum access system (SAS) controller, evolved node-b (enb) and method for allocation of shared spectrum
Embodiments of a Spectrum Access System (SAS) controller, Evolved Node-B (eNB) and methods for allocation of shared spectrum are disclosed herein. The SAS...
US-9,973,916 UE-based D2D discovery
In one embodiment, the present disclosure provides an evolved Node B (eNB) that includes a device-to-device (D2D) module configured to allocate at least one D2D...
US-9,973,915 Handover with ping pong avoidance in a wireless network
Generally, this disclosure provides apparatus and methods for improved handover with ping pong avoidance in wireless heterogeneous networks. The UE device may...
US-9,973,884 Device, system and method of controlling access to location sources
Some demonstrative embodiments include devices, systems and/or methods of controlling access to location sources. For example, a device may include a location...
US-9,973,758 Content adaptive entropy coding for next generation video
Techniques related to content adaptive entropy coding are described. A technique for video coding may include obtaining first and second video data for entropy...
US-9,973,757 Content adaptive predictive and functionally predictive pictures with modified references for next generation...
Techniques related to content adaptive predictive and functionally predictive pictures with modified references for next generation video coding are described.
US-9,973,752 Intelligent MSI-X interrupts for video analytics and encoding
Video analytics may be used to assist video encoding by selectively encoding only portions of a frame and using, instead, previously encoded portions....
US-9,973,527 Context-aware proactive threat management system
This disclosure is directed to a context-aware proactive threat management system. In general, a device may use internal activity data along with data about...
US-9,973,417 Method and apparatus for managing application state in a network interface controller in a high performance...
Methods related to communication between and within nodes in a high performance computing system are presented. Processing time for message exchange between a...
US-9,973,401 Service function path performance monitoring
Methods, systems, and storage media for monitoring service function path are disclosed herein. In an embodiment, a service function chain classifier module may...
US-9,973,370 Memory predistortion in bandwidth limited envelope tracking
An apparatus compensates nonlinearities in envelope tracking (ET) used in a mobile device by limiting a bandwidth of an envelope signal representing an envelope...
US-9,973,364 Generalized frequency division multiplexing (GFDM) frame strucutre for IEEE 802.11AY
In 60 GHz WiGig/IEEE 802.11ad, Orthogonal Frequency Division Multiplexing (OFDM) is used to achieve higher throughput. However, OFDM has one problem of high...
US-9,973,356 Slicer and decision feedback equalization circuitry
One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked...
US-9,973,335 Shared buffers for processing elements on a network device
Examples are disclosed for exchanging a key between an input/output device for network device and a first processing element operating on the network device....
US-9,973,315 Systems and methods for semi-persistent scheduling of wireless communications
Methods, systems, and devices for transmission and reception of SPS communications are disclosed herein. User equipment (UE) is configured to receive, in a...
US-9,973,207 Technologies for heuristic huffman code generation
Technologies for heuristic Huffman code generation include a computing device that generates a weighted list of symbols for a data block. The computing device...
US-9,973,176 Circuits for digital and analog controlled oscillators
A circuit may comprise a first node, a ring oscillator, a regulator, and a Kvcc compensation circuit. The first node may be a supply node to provide a supply...
US-9,972,686 Germanium tin channel transistors
Techniques related to transistors and integrated circuits having germanium tin, systems incorporating such transistors, and methods for forming them are...
US-9,972,642 High voltage three-dimensional devices having dielectric liners
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are...
US-9,972,616 Methods of forming tuneable temperature coefficient FR embedded resistors
Methods of forming resistor structures with tunable temperature coefficient of resistance are described. Those methods and structures may include forming an...
US-9,972,611 Stacked semiconductor package having fault detection and a method for identifying a fault in a stacked package
A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory...
US-9,972,610 System-in-package logic and method to control an external packaged memory device
Techniques and mechanisms for a SIP to control access to a non-volatile memory of another packaged device. In an embodiment, the SIP includes interface a...
US-9,972,601 Integrated circuit package having wirebonded multi-die stack
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first...
US-9,972,589 Integrated circuit package substrate with microstrip architecture and electrically grounded surface conductive...
Described herein are integrated circuit structures having a package substrate with microstrip architecture as the uppermost layers and a surface conductive...
US-9,972,541 Technique for filling high aspect ratio, narrow structures with multiple metal layers and associated configurations
Embodiments of the present disclosure describe techniques for filling a high aspect ratio, narrow structure with multiple metal layers and associated...
US-9,972,322 Speaker recognition using adaptive thresholding
Techniques related to speaker recognition are discussed. Such techniques may include determining an adaptive speaker recognition threshold based on a speech to...
US-9,972,313 Intermediate scoring and rejection loopback for improved key phrase detection
Techniques related to key phrase detection for applications such as wake on voice are discussed. Such techniques may include intermediate scoring of a state or...
US-9,972,131 Projecting a virtual image at a physical surface
Techniques for projecting virtual images are described herein. A plane of a surface may be identified, and a virtual image is projected onto the plane of the...
US-9,972,062 Parallel flood-fill techniques and architecture
Flood-fill techniques and architecture are disclosed. In accordance with one embodiment, the architecture comprises a hardware primitive with a software...
US-9,971,953 Visual recognition using deep learning attributes
A processing device for performing visual recognition using deep learning attributes and method for performing the same are described. In one embodiment, a...
US-9,971,912 Method, apparatus, and system for manageability and secure routing and endpoint access
A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints...
US-9,971,909 Method and apparatus for secure execution using a secure memory partition
A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor...
US-9,971,890 Securing thermal management parameters in firmware from cyber attack
Methods and systems may provide for identifying a thermal management setting in a computing system, and comparing the thermal management setting to valid...
US-9,971,711 Tightly-coupled distributed uncore coherent fabric
Selected portions of an uncore fabric of a system-on-a-chip (SoC) or other embedded system are divided into two independent pipelines. Each pipeline operates...
US-9,971,705 Virtual memory address range register
Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory...
US-9,971,703 Technologies for position-independent persistent memory pointers
Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing...
US-9,971,702 Nested exception handling
An example system that includes a processor and a memory device. The processor may include multiple execution units to execute instructions and a memory device...
US-9,971,691 Selevtive application of interleave based on type of data to be stored in memory
Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a...
US-9,971,688 Apparatus and method for accelerating operations in a processor which uses shared virtual memory
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an...
US-9,971,686 Vector cache line write back processors, methods, systems, and instructions
A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache...
US-9,971,685 Wear leveling based on a swapping operation between sets of physical block addresses of a non-volatile memory
A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical...
US-9,971,644 Serial I/O functional tester
One embodiment provides an apparatus. The apparatus includes a functional test controller. The functional test controller includes controller logic to receive...
US-9,971,627 Enabling maximum concurrency in a hybrid transactional memory system
In an embodiment of a transactional memory system, an apparatus includes a processor and an execution logic to enable concurrent execution of at least one first...
US-9,971,622 Technologies for application migration using lightweight virtualization
Technologies for migrating an application from a source computing device to a destination computing device using lightweight virtualization includes a migration...
US-9,971,615 Optimizing processor-managed resources based on the behavior of a virtual machine monitor
In one embodiment, a predefined behavior of a virtual machine monitor (VMM) with respect to one or more virtual machines (VMs) is identified, and...
US-9,971,603 Causing an interrupt based on event count
Some implementations provide techniques and arrangements for causing an interrupt in a processor in response to an occurrence of a number of events. A first...
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