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Patent # Description
US-1,029,7592 Monolithic three-dimensional (3D) ICs with local inter-level interconnects
Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least...
US-1,029,7567 Thermocompression bonding using plasma gas
Described herein are devices and techniques for thermocompression bonding. A device can include a housing, a platform, and a plasma jet. The housing can define...
US-1,029,7563 Copper seed layer and nickel-tin microbump structures
Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment,...
US-1,029,7549 Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact...
US-1,029,7542 Land side and die side cavities to reduce package z-height
A package structure including a capacitor mounted within a cavity in the package substrate is disclosed. The package structure may additionally include a die...
US-1,029,7541 Multiple-component substrate for a microelectronic device
Microelectronic devices having a multiple-component substrate assembly. A primary supports one or more integrated circuits, and an auxiliary substrate is...
US-1,029,7499 Method of forming a wrap-around contact on a semiconductor device
Techniques and methods related to forming a wrap-around contact on a semiconductor device, and apparatus, system, and mobile platform incorporating such...
US-1,029,7467 Self-aligned via and plug patterning for back end of line (BEOL) interconnects
Self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit...
US-1,029,7302 Magnetic storage cell memory with back hop-prevention
An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a...
US-1,029,7085 Augmented reality creations with interactive behavior and modality assignments
Systems, apparatuses and methods of creating virtual objects may provide for segmenting one or more objects in a scene and highlighting a selected object from...
US-1,029,7073 Method and apparatus for in-place construction of left-balanced and complete point K-D trees
Embodiments provide for a graphics processing apparatus including logic to receive data from an input buffer. The data can define a set of data points, where...
US-1,029,7047 Interleaved multisample render targets for lossless compression
One embodiment provides for a general-purpose graphics processor comprising a hardware graphics rendering pipeline configured to perform multisample...
US-1,029,7046 Techniques for reducing accesses for retrieving texture images
Various embodiments are generally directed to techniques for reducing storage access bandwidth requirements in retrieving a texture image from a storage for...
US-1,029,7002 Virtual touch pad method and apparatus for controlling an external display
An apparatus and method are described for using a touch screen device to control an external display. For example, one embodiment of an apparatus comprises a...
US-1,029,7001 Reduced power implementation of computer instructions
Systems and methods may provide a graphics processor that may identify operating conditions under which certain floating point instructions may utilize power to...
US-1,029,6871 Management of collaborative teams
Systems and methods for dynamically creating collaborative teams and managing collaborative work of a team are generally disclosed herein. One example...
US-1,029,6835 Automated quality assessment of physiological signals
Methods and systems may provide for receiving a physiological signal from a sensor configuration associated with a mobile device. A qualitative analysis may be...
US-1,029,6823 Methods, systems and computer program products for using a distributed associative memory base to determine...
Associative memory systems, methods and computer program products are provided. An associative memory system includes a distributed associative memory base...
US-1,029,6766 Technologies for secure enumeration of USB devices
Technologies for secure enumeration of USB devices include a computing device having a USB controller and a trusted execution environment (TEE). The TEE may be...
US-1,029,6660 Systems, apparatuses, and methods for feature searching
Detailed herein are embodiments of systems, methods, and apparatuses to be used for feature searching using an entry-based searching structure.
US-1,029,6605 Dictionary generation for example based image processing
Techniques related to generating dictionaries for example based image processing algorithms are discussed. Such techniques may include iteratively performing...
US-1,029,6489 Method and apparatus for performing a vector bit shuffle
A processor including a first vector register for storing a plurality of source data elements, a second vector register for storing a plurality of control...
US-1,029,6467 Securing writes to memory modules having memory controllers
A host central processing unit subsystem that writes information to external memory may provide policy to the external memory. Then every time a write comes...
US-1,029,6464 System, apparatus and method for dynamic profiling in a processor
In one embodiment, an apparatus includes: a storage having a plurality of entries each to store address information of an instruction and a count value of a...
US-1,029,6459 Remote atomic operations in multi-socket systems
Disclosed embodiments relate to remote atomic operations (RAO) in multi-socket systems. In one example, a method, performed by a cache control circuit of a...
US-1,029,6457 Reducing conflicts in direct mapped caches
A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an...
US-1,029,6432 Systems and methods for invasive debug of a processor without processor execution of instructions
Methods for invasive debug of a processor without processor execution of instructions are disclosed. As a part of a method, a memory mapped I/O of the processor...
US-1,029,6416 Read from memory instructions, processors, methods, and systems, that do not take exception on defective data
A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory...
US-1,029,6399 Data coherency model and protocol at cluster level
An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using...
US-1,029,6366 Virtualization exceptions
Embodiments of an invention for virtualization exceptions are disclosed. In one embodiment, a processor includes instruction hardware, control logic, and...
US-1,029,6347 Fusible instructions and logic to provide or-test and and-test functionality using multiple test sources
Fusible instructions and logic provide OR-test and AND-test functionality on multiple test sources. Some embodiments include a processor decode stage to decode...
US-1,029,6343 Hybrid atomicity support for a binary translation based microprocessor
A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first...
US-1,029,6342 Systems, apparatuses, and methods for cumulative summation
Systems, methods, and apparatuses for executing an instruction are described. For example, an instruction includes at least an opcode, a field for a packed data...
US-1,029,6338 System, apparatus and method for low overhead control transfer to alternate address space in a processor
In one embodiment, a processor includes: an accelerator associated with a first address space; a core associated with a second address space and including an...
US-1,029,6335 Apparatus and method for configuring sets of interrupts
An apparatus and method are described for efficiently processing and reassigning interrupts. For example, one embodiment of an apparatus comprises: a plurality...
US-1,029,6334 Method and apparatus for performing a vector bit gather
Apparatus, method, and system for performing a vector bit gather are describe herein. One embodiment of a processor includes: a first vector register storing...
US-1,029,6333 SIMD variable shift and rotate using control manipulation
Vector single instruction multiple data (SIMD) shift and rotate instructions are provided specifying: a destination vector register comprising fields to store...
US-1,029,6250 Method and apparatus for improving performance of sequential logging in a storage device
In one embodiment, an apparatus comprises a storage device to receive, from a computing host, a request to append data to a data log. The storage device is...
US-1,029,6246 Integrity protection for system management mode
Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode...
US-1,029,6238 Technologies for contemporaneous access of non-volatile and volatile memory in a memory device
Technologies for accessing memory devices of a memory module device includes receiving a memory read request form a host and reading, in response to the memory...
US-1,029,6224 Apparatus, system and method for increasing the capacity of a storage device available to store user data
Provided are an apparatus, system and method for using a validity table indicating whether physical addresses have valid data to optimize write and...
US-1,029,6217 Techniques to configure a solid state drive to operate in a storage mode or a memory mode
Examples are disclosed for configuring a solid state drive (SSD) to operate in a storage mode or a memory mode. In some examples, one or more configuration...
US-1,029,5406 Increased processing efficiency for optical spectral analyzers
An optical spectral analyzer for measuring an optical multi-channel signal by separating the multi-channel signal and measuring a plurality of single-channel...
US-1,029,5283 Thermal management using phase change material
Generally discussed herein are devices and methods for thermal management of a component. An apparatus can include a phase change material substantially at a...
US-1,029,4526 Polymer co-location in surface-attached biopolymers and arrays of biopolymers
Embodiments of the present invention provide substrates having controllably co-located polymers of different sequences. Methods are provided that allow the...
US-1,029,2607 Sensor data transmissions
Technology for a wearable heart rate monitoring device is disclosed. The wearable heart rate monitoring device can include a heart rate sensor operable to...
US-1,029,2188 Connection management techniques for wireless docking
Disclosed herein are connection management techniques for wireless docking. According to various such techniques, a wireless docking station may be arranged to...
US-1,029,2180 Apparatus, system and method of communicating non-cellular access network information over a cellular network
Some demonstrative embodiments include devices, systems and/or methods of communicating non-cellular access network information via a cellular network. For...
US-1,029,2143 Methods, apparatuses, and systems for enhancement of evolved physical downlink control channel for machine type...
Methods, systems, and storage media for monitoring enhanced physical downlink control channel (EPDCCH)-physical resource block (PRB) sets are described. In...
US-1,029,2044 Apparatus for end-user transparent utilization of computational, storage, and network capacity of mobile...
Mobile devices, systems, and methods for end-user transparent utilization of computational, storage, and network capacity of mobile device are described herein....
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