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Patent # Description
US-9,584,155 Look-ahead hash chain matching for data compression
Example data compression methods disclosed herein include determining a hash chain index corresponding to a first position in an input data buffer based on a...
US-9,584,139 Phase tracker for a phase locked loop
A phase locked loop includes a feedforward path receiving a reference signal having a reference frequency and outputting an output signal having an output...
US-9,583,973 Reducing power losses in a redundant power supply system
A power supply system includes at least a first power supply module and at least one redundant power supply module. The at least one power supply module...
US-9,583,828 Apparatus, system and method of controlling one or more antennas of a mobile device
Some demonstrative embodiments include apparatuses, devices, systems and/or methods for controlling an antenna scheme of one or more antennas. For example, a...
US-9,583,684 Edge coupling alignment using embedded features
Methods and systems may provide an alignment scheme for components that may reduce positional deviation between the components. The method may include placing a...
US-9,583,602 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and...
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling...
US-9,583,574 Epitaxial buffer layers for group III-N transistors on silicon substrates
Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon...
US-9,583,566 Reduced scale resonant tunneling field effect transistor
An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major...
US-9,583,491 CMOS nanowire structure
Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The...
US-9,583,487 Semiconductor device having metallic source and drain regions
Semiconductor devices having metallic source and drain regions are described. For example, a semiconductor device includes a gate electrode stack disposed above...
US-9,583,470 Electronic device with solder pads including projections
An electronic device including a solder pad structure and methods of forming an electrical interconnection are shown. Solder pads including one or more...
US-9,583,396 Making a defect free fin based device in lateral epitaxy overgrowth region
Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of...
US-9,583,390 Organic thin film passivation of metal interconnections
Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on...
US-9,583,389 Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD)
Selective area deposition of metal films by atomic layer deposition (ALD) and chemical vapor deposition (CVD) is described. In an example, a method of...
US-9,583,210 Fuse-based integrity protection
Various systems and methods for implementing fuse-based integrity protection are described herein. A system for validating a read-only memory (ROM), the system...
US-9,583,187 Multistage set procedure for phase change memory
Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for...
US-9,583,185 Phase change memory devices and systems having reduced voltage threshold drift and associated methods
Phase change memory devices, systems, and associated methods are provided and described. Such devices, systems, and methods manage and reduce voltage threshold...
US-9,583,182 Multi-level memory management
A multi-level memory management circuit can remap data between near and far memory. In one embodiment, a register array stores near memory addresses and far...
US-9,583,176 Variable weak leaker values during read operations
Systems, apparatuses and methods may provide for determining a status of an enable signal and selecting a leaker resistance from a plurality of leaker...
US-9,582,983 Low power voice trigger for finding mobile devices
Systems and methods may provide for monitoring an input audio signal from an onboard microphone of a mobile device while a host processor of the mobile device...
US-9,582,977 Systems and methods for monitoring consumption
A method monitors the consumption of materials, including determining the presence of materials in a smart receptacle using a sensor located in the smart...
US-9,582,924 Facilitating dynamic real-time volumetric rendering in graphics images on computing devices
A mechanism is described for facilitating dynamic real-time volumetric rendering of graphics images on computing devices. A method of embodiments, as described...
US-9,582,881 Machine vision image sensor calibration
A system, apparatus, method, and computer readable media for calibration of one or more extrinsic image sensor parameters. A system may calibrate a multi-camera...
US-9,582,858 Energy-efficient anti-aliasing
Anti-aliasing methods and systems may include logic to conduct a vertical blending weight determination based on horizontal pixel data associated with an image,...
US-9,582,853 Method and system of demosaicing bayer-type image data for image processing
Techniques related to demosaicing Bayer-type image data for image processing.
US-9,582,847 Color buffer compression
In accordance with some embodiments, a mask or table may be maintained to record information about whether or not each pixel within a tile is cleared. As used...
US-9,582,663 Detection of return oriented programming attacks
In one embodiment, a processor includes at least one execution unit and Return Oriented Programming (ROP) detection logic. The ROP detection logic may determine...
US-9,582,572 Personalized search library based on continual concept correlation
A system, devices, and methods for providing a personalized search library based on continual concept correlation include a client computing device and a...
US-9,582,464 Systems, apparatuses, and methods for performing a double blocked sum of absolute differences
Embodiments of systems, apparatuses, and methods for performing in a computer processor vector double block packed sum of absolute differences (SAD) in response...
US-9,582,463 Heterogeneous input/output (I/O) using remote direct memory access (RDMA) and active message
Methods and apparatus to provide heterogeneous I/O (Input/Output) using RDMA (Remote Direct Memory Access) and/or Active Message are described. In an...
US-9,582,454 Reconfigurable transmitter
Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended...
US-9,582,434 Enhanced security for accessing virtual memory
A disclosed method includes obtaining a physical address corresponding to a virtual address responsive to detecting a virtual address associated with a memory...
US-9,582,432 Instruction and logic for support of code modification in translation lookaside buffers
A processor includes a core with logic to execute a translated instruction. The translated instruction is translated from an instruction stored in a memory...
US-9,582,430 Asymmetric set combined cache
Embodiments are generally directed to an asymmetric set combined cache including a direct-mapped cache portion and a multi-way cache portion. A processor may...
US-9,582,422 Hardware prefetcher for indirect access patterns
Two techniques address bottlenecking in processors. The first is indirect prefetching. The technique can be especially useful for graph analytics and sparse...
US-9,582,357 Method and apparatus for treatment of state confidence data retrieved from a non-volatile memory array
Various embodiments are generally directed to an apparatus, method and other techniques to retrieve data from a non-volatile memory, and to read a memory cell...
US-9,582,339 Operation of software modules in parallel
Embodiments of computer-implemented methods, systems, computing devices, and computer-readable media (transitory and non-transitory) are described herein for...
US-9,582,332 Enabling a cloud to effectively assign workloads to servers
In accordance with some embodiments, a public infrastructure as a service (IaaS) user can provide a file, to a cloud service provider, with information about...
US-9,582,287 Processor having multiple cores, shared core extension logic, and shared core extension utilization instructions
An apparatus of an aspect includes a plurality of cores and shared core extension logic coupled with each of the plurality of cores. The shared core extension...
US-9,582,275 Method and apparatus for obtaining a call stack to an event of interest and analyzing the same
In one embodiment, a processor includes a performance monitor including a last branch record (LBR) stack to store a call stack to an event of interest, where...
US-9,582,216 Method and device to distribute code and data stores between volatile memory and non-volatile memory
A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes...
US-9,582,046 Locking hinge assembly for electronic device
In one embodiment an electronic device comprises a housing having a first section and a second section comprising a display coupled to the first section by a...
US-9,581,639 Organic space transformer attachment and assembly
Electronic device assemblies and methods including an organic substrate based space transformer are described. One assembly includes a space transformer...
US-9,580,776 Tungsten gates for non-planar transistors
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate...
US-9,579,067 Detection of a leading stroke risk indicator
Embodiments of a system and method for detecting a leading stroke risk indicator using low-cost, non-contact visual computing methods are generally described...
US-9,578,681 Methods and arrangements for a low power device in wireless networks
Some new low power architecture devices may, e.g., be associated with in a new device category in the IEEE 802.11ah Standard for devices with low power...
US-9,578,659 User equipment and method for contention-based communications over allocated PUSCH resources
Methods for contention-based transmission with contention-free feedback for reduced latency in LTE Advanced networks and an enhanced PUCCH are generally...
US-9,578,653 Network assisted parameter estimation in the presence of inter-cell interference
Embodiments provide improved interference classification and parameter estimation at a User Equipment (UE) that uses received scheduling information associated...
US-9,578,635 Method and apparatus for autonomous cluster head selection for machine-type-communications (MTC)
The present disclosure presents embodiments of a system and method for improved uplink transmission management in a network that includes one or more...
US-9,578,616 Forming carrier aggregation timing advance groups in a heterogeneous network
Technology for forming carrier aggregation timing advance groups in a heterogeneous network (HetNet) is disclosed. One method comprises assigning at least a...
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