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Patent # Description
US-9,935,722 Harmonic suppressing local oscillator signal generation
A transceiver includes local oscillator (LO) signal circuitry configured to output an LO signal having an LO frequency and mixer circuitry configured to input...
US-9,935,694 Reduction of user plane congestion
Technology for reducing user plane congestion is disclosed. An inquiry request message can be received at a mobility management entity (MME) from a congestion...
US-9,935,691 Antenna configuration for dynamic re-distribution of magnetic fields
Described herein are architectures, platforms and methods for dynamic re-distribution of magnetic fields in a device during near field communication (NFC)...
US-9,935,653 Enhanced cyclical redundancy check circuit based on galois-field arithmetic
Methods and apparatus related to enhanced Cyclical Redundancy Check (CRC) circuit based on Galois-Field arithmetic are described. In one embodiment, a plurality...
US-9,935,638 Validating an image for a reconfigurable device
A device includes a reconfigurable circuit and reconfiguration logic. The reconfiguration logic is to: receive, via a policy interface, a user policy and an...
US-9,935,615 RLS-DCD adaptation hardware accelerator for interference cancellation in full-duplex wireless systems
An adaptation hardware accelerator comprises a calculation unit to receive inputs at predefined time interval(s) that correspond to a calculation iteration, the...
US-9,935,590 Mixer impairment correction based on volterra series
Techniques for compensating for signal impairments introduced by a mixer are discussed. One example system employing such techniques can include mixer...
US-9,935,384 Circuit board with a connector having a latch that includes a latch frame, a latch slide, an ejector and a...
A circuit board may include a connector having a circuit module latch that may include a latch frame and pivot-able ejector assembly coupled to the latch frame.
US-9,935,353 Printed circuit board having a signal conductor disposed adjacent one or more trenches filled with a low-loss...
A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient...
US-9,935,205 Internal spacers for nanowire transistors and method of fabrication thereof
A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once...
US-9,935,191 High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer
A method including forming a barrier layer on a polar compound semiconductor layer on a sacrificial substrate; coupling the sacrificial substrate to a carrier...
US-9,935,107 CMOS FinFET device with dual strained cladding layers on relaxed SiGe fins, and method of fabricating the same
Techniques and methods related to dual strained cladding layers for semiconductor devices, and systems incorporating such semiconductor devices.
US-9,935,063 Rlink-on-die inductor structures to improve signaling
Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a...
US-9,935,036 Package assembly with gathered insulated wires
Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with...
US-9,935,033 Heat sink coupling using flexible heat pipes for multi-surface components
An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the...
US-9,935,002 Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a...
US-9,935,000 Slit stress modulation in semiconductor substrates
A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor...
US-9,934,976 Methods of forming low interface resistance rare earth metal contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a contact opening in an inter layer...
US-9,934,895 Spiral near field communication (NFC) coil for consistent coupling with different tags and devices
This document discloses one or more systems, apparatuses, methods, etc. for integrating a spiral near field communications (NFC) coil antenna to a portable...
US-9,934,859 Determining demarcation voltage via timestamps
In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at...
US-9,934,844 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual...
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in...
US-9,934,842 Multiple rank high bandwidth memory
Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory...
US-9,934,827 DRAM data path sharing via a split local data bus
Provided is memory device and a memory bank, comprising a global data bus, and a local data bus split into two parts, wherein the local data bus is configurable...
US-9,934,606 Deferred coarse pixel shading
A shading rate may be set by analyzing samples within a pixel. Then based on that analysis, a system determines whether to use coarse pixel, pixel or sample...
US-9,934,604 Culling using masked depths for MSAA
In accordance with some embodiments, a full per sample coverage mask may be used for a subset of the pixels in the tile, thereby enabling pixels that belong to...
US-9,934,573 Technologies for adjusting a perspective of a captured image for display
Technologies for adjusting a perspective of a captured image for display on a mobile computing device include capturing a first image of a user by a first...
US-9,934,386 Method and apparatus for managing the privacy and disclosure of location information
An approach for managing the privacy and disclosure of location information associated with a computer system. For one aspect, a request is received from a...
US-9,934,372 Technologies for performing orientation-independent bioimpedance-based user authentication
Technologies for performing orientation-independent bioimpedance-based user authentication include a compute device. The compute device includes a plurality of...
US-9,934,181 PCI express tunneling over a multi-protocol I/O interconnect
Described are embodiments of methods, apparatuses, and systems for PCIe tunneling across a multi-protocol I/O interconnect of a computer apparatus. A method for...
US-9,934,176 Transceiver multiplexing over USB type-C interconnects
An apparatus for transceiver multiplexing over USB Type-C interconnects is described herein. The apparatus includes a processor, a memory, a USB Type-C...
US-9,934,164 Memory write protection for memory corruption detection architectures
Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may...
US-9,934,158 System and methods exchanging data between processors through concurrent shared memory
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
US-9,934,155 Method, system, and apparatus for page sizing extension
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size,...
US-9,934,146 Hardware apparatuses and methods to control cache line coherency
Methods and apparatuses to control cache line coherency are described. A processor may include a first core having a cache to store a cache line, a second core...
US-9,934,143 Mapping a physical address differently to different memory devices in a group
A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a...
US-9,934,124 Implementation of processor trace in a processor that supports binary translation
In an embodiment, a processor includes execution logic to execute binary translated (BT) code that is translated from native architecture (NA) code. The...
US-9,934,090 Apparatus and method for enforcement of reserved bits
An apparatus and method are described for enforcement of reserved bits. For example, one embodiment of a processor comprises: a memory management unit to store...
US-9,934,088 Reduced uncorrectable memory errors
Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at...
US-9,934,082 Apparatus and method for detecting single flip-error in a complementary resistive memory
Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory...
US-9,934,072 Register file segments for supporting code block execution by using virtual cores instantiated by partitionable...
A system for executing instructions using a plurality of register file segments for a processor. The system includes a global front end scheduler for receiving...
US-9,934,062 Technologies for dynamically allocating hardware acceleration units to process data packets
Technologies for dynamically allocating acceleration units of a network device include a network device configured to determine a present compute usage value...
US-9,934,048 Systems, methods and devices for dynamic power management of devices using game theory
Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU,...
US-9,934,047 Techniques for switching between operating systems
Various embodiments are generally directed to an apparatus, method and other techniques for receiving information to invoke a transition from a first operating...
US-9,934,042 Method for dependency broadcasting through a block organized source view data structure
A method for dependency broadcasting through a block organized source view data structure. The method includes receiving an incoming instruction sequence using...
US-9,934,032 Processors, methods, and systems to implement partial register accesses with masked full register accesses
A method includes receiving a packed data instruction indicating a first narrower source packed data operand and a narrower destination operand. The instruction...
US-9,934,031 Read and write masks update instruction for vectorization of recursive computations over independent data
A processor executes a mask update instruction to perform updates to a first mask register and a second mask register. A register file within the processor...
US-9,933,968 Method, system, and device for modifying a secure enclave configuration without changing the enclave measurement
A system and method for adapting a secure application execution environment to support multiple configurations includes determining a maximum configuration for...
US-9,933,855 Augmented reality in a field of view including a reflection
Systems, apparatuses, and/or methods to augment reality. An object identifier may identify an object in a field of view of a user that includes a reflection of...
US-9,933,845 Apparatus and method to provide multiple domain clock frequencies in a processor
In an embodiment, a processor includes at least one core, a first domain to operate at a first clock frequency, and a second domain to operate at a second clock...
US-9,933,829 Methods and systems for server power line communication
A server system includes a common power bus, a power supply to provide direct current (DC) power through the common power bus, at least one node including a...
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