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Patent # Description
US-1,009,6328 Beamformer system for tracking of speech and noise in a dynamic environment
Techniques are provided for QR Decomposition (QRD) based minimum variance distortionless response (MVDR) adaptive beamforming. A methodology implementing the...
US-1,009,6321 Reverberation compensation for far-field speaker recognition
Techniques are provided for reverberation compensation for far-field speaker recognition. A methodology implementing the techniques according to an embodiment...
US-1,009,6165 Technologies for virtual camera scene generation using physical object sensing
Technologies for virtual camera scene generation include a computing device and one or more physical objects. The computing device determines a physical...
US-1,009,6163 Haptic augmented reality to reduce noxious stimuli
Systems, apparatuses and methods may provide for classifying a physical proximity event with respect to a wearable device based on one or more of a haptic input...
US-1,009,6149 Direct motion sensor input to rendering pipeline
System and techniques for direct motion sensor input to rendering pipeline are described herein. A view parameter may be received, via an input port to a...
US-1,009,6080 Power optimization with dynamic frame rate support
A frame of pixel data may be burst at a higher frame rate to create a lower effective refresh rate when the actual image update rate is lower than the frame...
US-1,009,5996 Probabilistic inventory RFID method and system
A radio frequency identification (RFID) system for monitoring a space is disclosed. The system may include a controller connected with a plurality of RFID...
US-1,009,5793 Collection and management of precision user preference data
Methods and systems may involve storing device-specific user preference data to a local device and receiving a real-time request from a remote device. One or...
US-1,009,5653 Apparatuses, systems, and methods for accurately measuring packet propagation delays through USB retimers
Methods and apparatuses relating to measuring propagation delays through USB retimers are described. In one embodiment, a retimer apparatus includes a receiver...
US-1,009,5629 Local and remote dual address decoding using caching agent and switch
Generally discussed herein are systems, devices, and methods for local and remote dual address decoding. According to an example a node can include one or more...
US-1,009,5623 Hardware apparatuses and methods to control access to a multiple bank data cache
Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to...
US-1,009,5622 System, method, and apparatuses for remote monitoring
Embodiments of systems, method, and apparatuses for remote monitoring are described. In some embodiments, an apparatus includes at least one monitoring circuit...
US-1,009,5618 Memory card with volatile and non volatile memory space having multiple usage model configurations
An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory...
US-1,009,5573 Byte level granularity buffer overflow detection for memory corruption detection architectures
Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of...
US-1,009,5557 System and method to provide single thread access to a specific memory region
Processing logic and a method to provide single thread access to a specific memory region without suspending processing activity for all other cores and/or...
US-1,009,5522 Instruction and logic for register based hardware memory renaming
A processor includes a core, a memory subsystem, a predictor module, and a memory rename module. The predictor module may include a first logic to identify a...
US-1,009,5521 Apparatus and method for low-latency invocation of accelerators
An apparatus and method are described for providing low-latency invocation of accelerators. For example, a processor according to one embodiment comprises...
US-1,009,5520 Interrupt return instruction with embedded interrupt service functionality
An instruction pipeline implemented on a semiconductor chip is described. The semiconductor chip includes an execution unit having the following to execute an...
US-1,009,5517 Apparatus and method for retrieving elements from a linked structure
An apparatus and method are described for retrieving elements from a linked structure. For example, one embodiment of an apparatus comprises: a decode unit to...
US-1,009,5516 Vector multiplication with accumulation in large register space
An apparatus is described having an instruction execution pipeline that has a vector functional unit to support a vector multiply add instruction. The vector...
US-1,009,5515 Compressed instruction format
A technique for decoding an instruction in a variable-length instruction set. In one embodiment, an instruction encoding is described, in which legacy, present,...
US-1,009,5480 Automatic code generation for crowdsourced automatic data collection
An automatic code generator that may be located at a server may generate code to handle crowdsourced data. The crowdsourced data may come from members of the...
US-1,009,5461 Outside-facing display for head-mounted displays
Devices and methods disclosed herein may include a system for a multiple screen head-mounted display. The system includes a first transceiver to obtain a first...
US-1,009,5437 Memory access control
The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory...
US-1,009,5432 Power management and monitoring for storage devices
In one embodiment, a command for a storage device may be received, wherein the command comprises a plurality of stages. Power for the plurality of stages of the...
US-1,009,5424 Apparatus and method for programming non-volatile memory using a multi-cell storage cell group
Provided are an apparatus, method, and system for programming a multi-cell storage cell group. A non-volatile memory has storage cells. Each storage cell is...
US-1,009,5302 Method and apparatus for automatic adaptive voltage control
A processing device includes a power management unit to receive a base clock (BCLK) frequency rate to be applied to the processing device; and to determine,...
US-1,009,5300 Independent power control of processing cores
Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least...
US-1,009,0892 Apparatus and a method for data detecting using a low bit analog-to-digital converter
An apparatus and a method for detecting data transmitted over a wireless channel are disclosed. For example, for each receive antenna of a plurality of receive...
US-1,009,0713 Multiple coils for wireless power
A wireless power transfer device and method including a first coil of wire having a first winding to receive electrical current and emit a first electromagnetic...
US-1,009,0383 Column IV transistors for PMOS integration
Techniques are disclosed for forming column IV transistor devices having source/drain regions with high concentrations of germanium, and exhibiting reduced...
US-1,009,0313 NAND memory array with mismatched cell and bitline pitch
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mismatched cell and bitline pitch....
US-1,009,0304 Isolation well doping with solid-state diffusion sources for FinFET architectures
An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that...
US-1,009,0277 3D integrated circuit package with through-mold first level interconnects
3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package...
US-1,009,0261 Microelectronic package debug access ports and methods of fabricating the same
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment,...
US-1,009,0259 Non-rectangular electronic device components
Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a...
US-1,009,0239 Metal-insulator-metal on-die capacitor with partial vias
A Metal-Insulator-Metal on-die capacitor is described with partial vias. In one example, first and second power grid layers are formed in a semiconductor die....
US-1,009,0034 Magnetoelectric memory cells with domain-wall-mediated switching
A magnetoelectric memory cell with domain-wall-mediated switching is implemented using a split gate architecture. The split gate architecture allows a domain...
US-1,008,9964 Graphics processor logic for encoding increasing or decreasing values
Embodiments provide for a graphics processing apparatus comprising a graphics processing unit including bounding volume logic to encode a first bounding volume...
US-1,008,9962 Display interface partitioning
Various embodiments are generally directed to techniques to partition a display interface such that pixel data associated with display data having indications...
US-1,008,9779 Apparatus and method for conservative rasterization of polygons
An apparatus and method are described for conservative rasterization. For example, one embodiment of a graphics processing apparatus comprises: an edge tagging...
US-1,008,9750 Method and system of automatic object dimension measurement by using image processing
A system, article, and method of automatic object dimension measurement by using image processing.
US-1,008,9696 Budget-aware event information collection during program execution
Embodiments of techniques and systems for slowdown-budget-aware event information collection are described. In various embodiments, a system may be configured...
US-1,008,9500 Secure modular exponentiation processors, methods, systems, and instructions
A processor of an aspect includes a decode unit to decode a modular exponentiation with obfuscated input information instruction. The modular exponentiation...
US-1,008,9447 Instructions and logic to fork processes of secure enclaves and establish child enclaves in a secure enclave...
Instructions and logic fork processes and establish child enclaves in a secure enclave page cache (EPC). Instructions specify addresses for secure storage...
US-1,008,9270 Interchangeable power and signal contacts for IO connectors
Systems and methods of interconnecting devices may include an input/output (IO) connector assembly having a voltage regulator, one or more signaling circuits, a...
US-1,008,9264 Callback interrupt handling for multi-threaded applications in computing environments
A mechanism is described for facilitating callback interrupt handling for multi-threaded applications in computing environments. A method of embodiments, as...
US-1,008,9263 Synchronization of interrupt processing to reduce power consumption
A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first...
US-1,008,9247 System and method for coupling a host device to secure and non-secure devices
One embodiment provides an apparatus. The apparatus includes an input output memory management unit (I/O MMU), a non-secure operating system (OS) driver, a...
US-1,008,9244 Hardware for miss handling from a translation protection data structure
A processor includes a memory to store original code and a fingerprint data structure, which stores, in a way thereof, an entry including a physical address for...
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