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Patent # Description
US-7,885,313 Method and apparatus for cooperative coexistence between wireless communication protocols
A method and apparatus of reducing interference between subsystems implementing wireless communication protocols is disclosed. The method comprises reducing...
US-7,885,287 Method and apparatus for adaptive network allocation
A method and apparatus for adaptive network allocation are described herein. In some embodiments, a node may receive a request-to-send (RTS) packet that includes...
US-7,885,220 Method and apparatus for improved dual channel operation and access point discovery in wireless communication...
A method and apparatus of coordinating Time Division Multiple Access operation of wireless communication devices is disclosed. The method comprises an access...
US-7,885,214 Device, system, and method for partitioning and framing communication signals in broadband wireless access networks
A method and system for partitioning frames into sub-frames, where the frames may be defined according to a reference system standard, and transmitting one or...
US-7,885,210 Accounting for map parsing delay to enable coexistence of multiple radios
In general, in one aspect, the disclosure describes an apparatus that includes a first radio to communicate with a first wireless network and a second radio to...
US-7,885,197 System and method for measuring per node packet loss in a wireless network
A method and system for configuring a wireless network, e.g., an ad hoc wireless network having a plurality of nodes and at least one server. In the wireless...
US-7,885,178 Quasi-parallel multichannel receivers for wideband orthogonal frequency division multiplexed communications and...
A quasi-parallel receiver may simultaneously receive signals within several subchannels that comprise a wideband channel. The receiver includes a subchannel...
US-7,885,099 Adaptive wordline programming bias of a phase change memory
The leakage current and power consumption of phase change memories may be reduced using adaptive word line biasing. Depending on the particular voltage applied...
US-7,884,865 High speed noise detection and reduction in active pixel sensor arrays
A system for detecting high speed noise in active pixel sensors includes a photodiode for receiving low levels of light, a reset transistor, an amplifier...
US-7,884,858 Object trackability via parametric camera tuning
A method and apparatus are described for improving object trackability via parametric camera tuning. In one embodiment, a determination is made as to whether the...
US-7,884,695 Low resistance inductors, methods of assembling same, and systems containing same
A low-resistance inductor is made from a plurality of first inter-abutting insulated electrode coil sub-segments that is coupled to a plurality of second...
US-7,884,499 Intervention of independent self-regulation of power consumption devices
Methods and apparatuses for intervening in the self power or thermal regulations of a plurality of independent power consumption devices are described herein....
US-7,884,470 Semiconductor packages with stiffening support for power delivery
Embodiments of the invention relate to semiconductor packages in which electrical power is delivered to die-side components removably installed in sockets formed...
US-7,884,354 Germanium on insulator (GOI) semiconductor substrates
Germanium on insulator (GOI) semiconductor substrates are generally described. In one example, a GOI semiconductor substrate comprises a semiconductor substrate...
US-7,883,951 CMOS device with metal and silicide gate electrodes and a method for making it
A semiconductor device and a method for forming it are described. The semiconductor device comprises a metal NMOS gate electrode that is formed on a first part...
US-7,882,634 Method of manufacturing heat sink using clad metal
According to some embodiments, an outer metal is cladded to a core metal to create a cladded heat sink fin, the cladded heat sink fin is inserted in a groove of...
US-7,882,628 Multi-chip packaging using an interposer such as a silicon based interposer with through-silicon-vias
The formation of electronic assemblies is described. One embodiment includes providing a body and forming a first metal pad layer on a first surface thereof. A...
US-7,882,624 Method of forming electronic package having fluid-conducting channel
To accommodate high power densities associated with high-performance integrated circuits, an integrated circuit (IC) package includes a heat-dissipating...
US-7,882,545 Secure wireless network
A method is used to authenticate a wireless device for secure operation on a wireless local area network, the wireless local area network including a controller....
US-7,882,498 Method, system, and program of a compiler to parallelize source code
Provided are a method, system, and program for parallelizing source code with a compiler. Source code including source code statements is received. The source...
US-7,882,415 3-Stripes gilbert low density parity-check codes
A method and apparatus are provided for a coding process of a communication signal. A 3-stripes parity-check matrix is generated from a parity-check matrix of a...
US-7,882,381 Managing wasted active power in processors based on loop iterations and number of instructions executed since...
Methods of managing wasted active power of processors in computer systems and other electronic devices are disclosed. In one aspect, a method may include...
US-7,882,341 System and method to enable parallelization of early platform initialization
In some embodiments, the invention involves reducing the time required for a platform to boot to its target application/operating-system using parallelization of...
US-7,882,339 Primitives to enhance thread-level speculation
A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more...
US-7,882,325 Method and apparatus for a double width load using a single width load port
A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a...
US-7,882,318 Tamper protection of software agents operating in a vitual technology environment methods and apparatuses
Methods, apparatuses, articles, and systems for comparing a first security domain of a first memory page of a physical device to a second security domain of a...
US-7,882,311 Non-snoop read/write operations in a system supporting snooping
Techniques that may utilize generic tracker structures to provide data coherency in a multi-node system that supports non-snoop read and write operations. The...
US-7,882,255 Method and apparatus for maintaining local area network ("LAN") and wireless LAN ("WLAN") security associations
Cooperating entities share a signaling interface. Each entity establishes a security association between itself and an endpoint, and one of the entities...
US-7,881,698 Network based archiving of user-specific information in a communication system
User-specific information (e.g., call log information, contact information, etc.) normally stored within a mobile user device associated with a user is also...
US-7,881,614 Optically connecting computer components
A central component of a processor based system, the central component including a processor and an optical interface to transmit data encoded as an optical...
US-7,881,475 Systems and methods for negotiating security parameters for protecting management frames in wireless networks
Systems and methods provide a mechanism for wireless stations and access points to negotiate security parameters for protecting management frames. The access...
US-7,881,470 Network mobility security management
A node that couples to the Internet establishes a secure connection with another node that couples to the Internet. The secure connection to be established via...
US-7,881,391 OFDM receiver and method for decoding OFDM symbols of two or more data streams with reduced multiplication...
Embodiments of an OFDM receiver and methods for decoding OFDM symbols of two or more data streams with reduced multiplication operations are generally described...
US-7,881,390 Increased discrete point processing in an OFDM communication system
Methods and apparatus provide increased symbol length with more subcarriers in a fixed-bandwidth system. The subcarriers spacing may be reduced to provide...
US-7,881,341 Reconfigurable media controller to accommodate multiple data types and formats
A media controller is reconfigurable to handle different formats and types of data. In one embodiment, the invention includes a media access controller coupled...
US-7,880,837 Black and white color cholesteric liquid crystal display
A cholesteric display may be formed, in some embodiments, using a single display element to produce multi-colors for display. A cholesteric material may be...
US-7,880,310 Direct device attachment on dual-mode wirebond die
A dual-mode integrated circuit comprises wirebondable and solderable electrical connectors.
US-7,880,284 Embedded power gating
With embodiments disclosed herein, the distribution of gated power is done using on-die layers without having to come back out and use package layers.
US-7,880,231 Integration of a floating body memory on SOI with logic transistors on bulk substrate
A method and the resultant memory is described for forming an array of floating body memory cells and logic transistors on an SOI substrate. The floating bodies...
US-7,880,124 Assembly packaging using induction heating
An embodiment of the present invention is a technique to package a device. Heat is localized on a die having bumps on a package substrate using a first induction...
US-7,879,764 Electrically active combinatorial chemical (EACC) chip for biochemical analyte detection
Apparatus and methods are disclosed for electrically active combinatorial-chemical (EACC) chips for biochemical analyte detection. An apparatus includes a...
US-7,879,739 Thin transition layer between a group III-V substrate and a high-k gate dielectric layer
Embodiments of the invention provide a method to form a high-k dielectric layer on a group III-V substrate with substantially no oxide of the group III-V...
US-7,879,675 Field effect transistor with metal source/drain regions
A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed...
US-7,878,016 Device and method for on-die temperature measurement
A system for measuring and managing thermal operations of a processor core on a semiconductor die using a sensor positioned in a hotspot of the processor core. A...
US-7,877,666 Tracking health of integrated circuit structures
Methods and apparatus to track the health of integrated circuit structures are described. In an embodiment, a counter may be updated when the status of a portion...
US-7,877,589 Configuring a device for operation on a computing platform
A method which includes initializing a device following a power cycle. The initialization includes an agent for the device implementing one or more command...
US-7,877,583 Method and apparatus for assigning thread priority in a processor or the like
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread...
US-7,877,519 Selecting one of a plurality of adapters to use to transmit a packet
Provided are a method, system, and program for selecting one of a plurality of adapters to use to transmit a packet. A packet is generated by a protocol driver...
US-7,877,504 Techniques for entry lookups
Techniques to store entries so that minimal sequential memory accesses are used to determine all relevant entries. Entries may be grouped into blocks. The order...
US-7,877,339 Method and system of creating an approximate kernel matrix to train a kernel machine
A method and system of creating an approximate kernel matrix to train a kernel machine. In one embodiment of the invention, a set of kernel machine training data...
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