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Patent # Description
US-7,725,745 Power aware software pipelining for hardware accelerators
Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a...
US-7,725,713 Launching a secure kernel in a multiprocessor system
In one embodiment of the present invention, a method includes verifying an initiating logical processor of a system; validating a trusted agent with the...
US-7,725,662 Hardware acceleration for a software transactional memory system
A method and apparatus for accelerating transactional execution. Barriers associated with shared memory lines referenced by memory accesses within a transaction...
US-7,725,657 Dynamic quality of service (QoS) for a shared cache
In one embodiment, the present invention includes a method for associating a first priority indicator with data stored in a first entry of a shared cache memory...
US-7,725,645 Dual use for data valid signal in non-volatile memory
In some types of non-volatile memory devices, the same signal from a memory device may be used for two purposes: During a read operation, the signal may be used...
US-7,725,637 Methods and apparatus for generating system management interrupts
A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a...
US-7,725,624 System and method for cryptography processing units and multiplier
In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one...
US-7,725,608 Enabling and disabling device images on a platform without disrupting BIOS or OS
Device images, for example IDE mass storage device images, may be enabled and disabled without disrupting a host system. In one embodiment, the invention...
US-7,725,573 Methods and apparatus for supporting agile run-time network systems via identification and execution of most...
Methods and apparatus for supporting agile run-time network systems via identification and execution of most efficient application binary code in view of...
US-7,725,521 Method and apparatus for computing matrix transformations
A method and apparatus for performing matrix transformations including multiply-add operations and byte shuffle operations on packed data in a processor. In one...
US-7,725,511 Bio-metric input mechanism
A biometric keyboard or other input device, such as a keypad or touch screen, may be part of an input mechanism for inputting user information to a computing...
US-7,725,118 Multi-radio wireless communication device and method for coordinating communications between potentially...
Embodiments of a multi-radio wireless communication device having a Worldwide Interoperability for Microwave Access (WiMax) radio module and a Bluetooth (BT)...
US-7,725,115 Paging operation for idle mode terminals with a plurality of wireless interfaces
Embodiments of the present invention provide paging operations for idle mode terminals with a plurality of wireless interfaces. In accordance with an embodiment,...
US-7,725,094 Power prioritization among functions of a multi-function device
A device can provide a first function and a second function. The first function can have a higher priority for power than the second function. An input element...
US-7,725,093 Method and apparatus for a power-efficient framework to maintain data synchronization of a mobile personal...
An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment,...
US-7,725,085 Space-time communications determination
Apparatus and systems, a well as methods and articles, may operate to determine whether to communicate using a space-time communications technique responsive to...
US-7,724,858 Techniques to manage latency for multiple receivers
Method and apparatus to manage delay for multiple receivers for a wireless system are described.
US-7,724,847 Techniques for reduction of delayed reflection inter-symbol interference
Techniques are described to reduce delayed reflection inter-symbol interference (ISI) in signals. In some implementations, a channel reflection canceller is...
US-7,724,748 LAN emulation over infiniband fabric apparatus, systems, and methods
A method and device for local area network (LAN) emulation over an Infiniband (IB) fabric. An IB LAN driver at a first node on an IB fabric receives the port and...
US-7,724,683 Arrangements for controlling multiple MAC interfaces
Arrangements for controlling multiple media access control interfaces are disclosed. In one embodiment a method for controlling the interfaces can include...
US-7,724,671 Architecture for resource management in a telecommunications network
An architecture for resource management in a telecommunications network includes two or more nodes connected over a logically direct path in a peer-to-peer...
US-7,724,645 Method and apparatus for serial link down detection
An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a...
US-7,724,542 Reworkable RF shield
Certain embodiments relate to electronic devices and methods for forming electronic devices having a component shielded by a reworkable RF shield. The RF shield...
US-7,724,498 Low inductance capacitors, methods of assembling same, and systems containing same
A low-inductance capacitor exhibits a first characteristic inductance during use in a first capacitor subsection and a second characteristic inductance during...
US-7,724,264 Calculating display mode values
Values are calculated which control the manner in which a display streamer directs the movement of display data. The values are stored in the display streamer.
US-7,724,136 Revealable RFID devices
The antenna of a radio frequency identification (RFID) tag may be detuned by applying a conductive material in radio frequency (RF) contact with the antenna,...
US-7,724,078 Adjusting PLL/analog supply to track CPU core supply through a voltage regulator
A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the...
US-7,723,951 Battery charging apparatus having a chute and method of recharging a battery
The embodiments of the invention relate to a novel apparatus and method for a battery charging system in a shared environment, as well as for monitoring battery...
US-7,723,841 Thermal spacer for stacked die package thermal management
In some embodiments, a thermal spacer for stacked die package thermal management is presented. In this regard, an apparatus is introduced having a top integrated...
US-7,723,819 Granular magnetic layer with planar insulating layer
An embodiment of the present invention is a technique to fabricate a device using a magnetic layer. A magnetic layer having granular magnetic particles is...
US-7,723,759 Stacked wafer or die packaging with enhanced thermal and device performance
An apparatus includes a metallization region including a plurality of metal layers on a device layer of a substrate, a via extending through the substrate and...
US-7,723,749 Strained semiconductor structures
A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium...
US-7,723,618 Shifted segment layout for differential signal traces to mitigate bundle weave effect
An article of manufacture includes a circuit board and a pair of traces on or in the circuit board. The pair of traces includes a first trace and a second trace....
US-7,723,208 Integrated re-combiner for electroosmotic pumps using porous frits
Trenches may be formed in the upper surfaces of a pair of wafers. Each trench may be coated with a catalyst that is capable of removing oxygen or hydrogen from a...
US-7,723,164 Dual heat spreader panel assembly method for bumpless die-attach packages, packages containing same, and...
A process includes mating a first heat spreader and a second heat spreader, such that the first heat spreader at a mating surface and second heat spreader at a...
US-7,723,160 Thermal interface structure with integrated liquid cooling and methods
A method and device for thermal conduction is provided. A thermal interface device and method of formation is described that includes advantages such as improved...
US-7,723,008 Photoactive adhesion promoter in a slam
A semiconductor process technique to help reduce semiconductor process effects, such as undesired line edge roughness, insufficient lithographical resolution,...
US-RE41,355 Method for placing active circuits beneath active bonding pads
The present invention provides a bonding pad structure for integrated circuit devices which allows the active circuits to be placed under bonding pads of the...
US-7,721,150 Failover and load balancing
Provided are techniques for failover when at least one of a first network adapter and a data path through the first network adapter fails, wherein the first...
US-7,721,148 Method and apparatus for redirection of machine check interrupts in multithreaded systems
Disclosed is a communication mechanism among hardware, firmware and system software in order to redirect interrupts or other hardware events to only one thread...
US-7,721,129 Method and apparatus for reducing clock frequency during low workload periods
A clock frequency control unit for an integrated circuit (IC) includes a clock generator, a finite state machine (FSM), and a gating circuit (GC). The FSM has at...
US-7,721,080 Management of option ROM
Provided are a method, system, and article of manufacture, wherein instructions stored in an option ROM are copied to the system memory of a computer, wherein...
US-7,721,077 Performing endian conversion
A computing system may support an endian toggle register (ETR) and the endianess of the endian toggle register may be designated using a set endian bit (SEB) or...
US-7,721,076 Tracking an oldest processor event using information stored in a register and queue entry
Method, apparatus and system embodiments provide a register to track the oldest exception event or sticky event in a processor. The processor may be an...
US-7,721,060 Method and apparatus for maintaining data density for derived clocking
Some embodiments of the invention implement point-to-point memory channels that virtually eliminate the need for mandatory synchronization cycles for a derived...
US-7,721,051 Techniques to improve cache performance
Method and apparatus to improve cache performance using interarrival times between demand requests are described.
US-7,721,050 Re-snoop for conflict resolution in a cache coherency protocol
In a cache coherency protocol a re-snoop may be utilized to resolve a data request conflict condition. The re-snoop may avoid a conflict resolution phase, which...
US-7,721,041 PSRAM and method for operating thereof
Disclosed is a pseudo static random access memory (PSRAM) and a method for operating the same. The PSRAM includes a multi-bit control register and a multiplexer...
US-7,721,013 Communicating graphics data via an out of band channel
In one embodiment, the present invention includes a method for providing a command from a keyboard, video and mouse (KVM) system of a first system to a graphics...
US-7,720,930 Systems and methods using NIC-based prefetching for host TCP context lookup
Systems and methods using network interface card-based (NIC-based) prefetching for host TCP context lookup are disclosed. The process generally includes hashing,...
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