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Patent # Description
US-7,924,596 Area efficient programmable read only memory (PROM) array
A programmable ROM (PROM) architecture includes cascode NMOS transistors with a fuse bit cell that is arrayed, with sleep transistors located in each column of...
US-7,924,122 Collapsible contact switch
Embodiments of the invention describe a contact switch, which may include a bottom electrode structure including a bottom actuation electrode and a top...
US-7,923,760 Dielectric spacers for metal interconnects and method to form the same
A plurality of metal interconnects incorporating dielectric spacers and a method to form such dielectric spacers are described. In one embodiment, the...
US-7,923,240 Photo-activated field effect transistor for bioanalyte detection
The application relates to a device and method for performing analyte detection, especially biomolecule detection. The device and method combine photo-induced...
US-7,923,237 Method and apparatus for combined electrochemical synthesis and detection of analytes
Described are devices and methods for detecting binding on an electrode surface. In addition, devices and methods for electrochemically synthesizing polymers...
US-7,923,125 Apparatus for solder crack deflection
An apparatus that includes a first component defining an interior of the apparatus; a first solder composition exterior to the first component; a second solder...
US-7,923,059 Method of enabling selective area plating on a substrate
A method of enabling selective area plating on a substrate includes forming a first electrically conductive layer (310) over substantially all of the substrate,...
US-7,921,463 Methods and apparatus for providing an insertion and integrity protection system associated with a wireless...
Embodiments of methods and apparatus for providing an insertion and integrity protection system associated with a wireless communication platform are generally...
US-7,921,453 Authenticated distributed detection and inference
Embodiments of the present invention provide apparatuses, methods, and systems for authenticated distributed detection and inference. In various embodiments, an...
US-7,921,349 Mode selection for data transmission in wireless communication channels based on statistical parameters
A method and communication system for selecting a mode for encoding data for transmission in a wireless communication channel between a transmit unit and a...
US-7,921,293 Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment
An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a...
US-7,921,280 Selectively powered retirement unit using a partitioned allocation array and a partitioned writeback array
In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array...
US-7,921,276 Applying quality of service (QoS) to a translation lookaside buffer (TLB)
In one embodiment, the present invention includes a translation lookaside buffer (TLB) having storage locations each including a priority indicator field to...
US-7,921,253 Cache coherent switch device
In one embodiment, the present invention includes a switch device to be coupled between a first semiconductor component and a processor node by interconnects of...
US-7,921,251 Globally unique transaction identifiers
In one embodiment of the present invention, a method includes identifying a transaction from a first processor to a second processor of a system with a...
US-7,921,155 Method and apparatus for peer-to-peer services
A method and apparatus for peer-to-peer services have been described.
US-7,920,897 Interference suppression in computer radio modems
The present invention can reduce interference generated by processors and other computing devices when a connected radio is active. In one embodiment, the...
US-7,920,649 Recovering precoded data using a Mueller-Muller recovery mechanism
In one embodiment, the present invention includes an apparatus having a digital signal processor (DSP) coupled to receive a digitized signal. The DSP may be...
US-7,920,554 Supporting both packet and circuit-based wireless networks
Middleware may accommodate both packet data and circuit data services in the same cellular telephone. A cellular telephone may travel between networks that are...
US-7,920,483 System and method of dynamically optimizing a transmission mode of wirelessly transmitted information
The present invention includes a method of optimizing a transmission mode of wirelessly transmitted data. The method includes selecting a first transmission...
US-7,920,470 Network adapter with TCP support
A network adapter and corresponding method for its use are disclosed. The network adapter has an operational mode that allows a host CPU to offload transmission...
US-7,920,419 Isolated P-well architecture for a memory device
A memory device and a method to prevent or reduce program disturb by isolating P-wells of strings in a non-volatile memory array. During a program operation,...
US-7,919,984 System and apparatus of reconfigurable transceiver design for multi-mode signaling
A reconfigurable transceiver is claimed for a wide range of I/O systems. The reconfigurable transmitter of the reconfigurable transceiver is capable of...
US-7,919,859 Copper die bumps with electromigration cap and plated solder
Embodiments of the invention include apparatuses and methods relating to copper die bumps with electtomigration cap and plated solder. In one embodiment, an...
US-7,919,408 Methods for fabricating fine line/space (FLS) routing in high density interconnect (HDI) substrates
A method for fabricating fine line and space routing described. The method includes providing a substrate having a dielectric layer and a seed layer disposed...
US-7,919,377 Contactless flash memory array
A method for forming a contactless flash memory cell array is disclosed. According to an embodiment of the invention, a plurality of active regions is formed on...
US-7,917,910 Techniques to manage critical region interrupts
Briefly, techniques to manage interrupts and swaps of threads operating in critical region. In an embodiment, a thread is to be interrupted during a first...
US-7,917,898 Methods and apparatus to provide a modular native method invocation system
Methods and apparatus to provide a modular native method invocation (NMI) system are described herein. In an example method, first NMI information associated...
US-7,917,828 Providing error correction coding for probed data
In one embodiment, the present invention includes a method for receiving an error correction code for information from a first port of a first agent and...
US-7,917,823 Decoupled clocking in testing architecture and method of testing
A test architecture and method of testing are disclosed to allow multiple scan controllers, which control different scan chain designs in multiple logic blocks,...
US-7,917,789 System and method for selecting optimal processor performance levels by using processor hardware feedback...
An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor...
US-7,917,787 Method, apparatus and system to dynamically choose an aoptimum power state
Some embodiments of the invention include an apparatus and method for dynamically choosing an optimum power state. In some embodiments, the optimum power state...
US-7,917,734 Determining length of instruction with multiple byte escape code based on information from other than opcode byte
A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of...
US-7,917,724 Protection of user-level applications based on page table information
In one embodiment, the present invention includes a virtual machine monitor (VMM) to access a protection indicator of a page table entry (PTE) of a page of a set...
US-7,917,689 Methods and apparatuses for nonvolatile memory wear leveling
Apparatuses, systems, and computer program products that enable wear leveling of nonvolatile memory devices, such as flash memory devices, are disclosed. One or...
US-7,917,646 Speculative distributed conflict resolution for a cache coherency protocol
A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors...
US-7,917,509 String search scheme in a distributed architecture
Methods and apparatuses for searching network data for one or more predetermined strings are disclosed. In one embodiment, the string search is a multi-stage...
US-7,916,965 Detection of artifacts resulting from image signal decompression
A method includes making a first determination as to whether a current pixel has a value which reflects a mosquito noise artifact, and determining whether to...
US-7,916,750 Transaction layer packet compression
A system, method, and device are disclosed. In one embodiment, the device comprises logic to determine whether a received transaction layer packet (TLP) has a...
US-7,916,670 Apparatus and method of block acknowledgements with reduced recipient state information
An apparatus and method for block acknowledgements with reduced recipient state information are described. In one embodiment, the method comprises the storing of...
US-7,916,518 VCC control inside data register of memory device
A memory device including current-limiting circuitry coupled to a first inverter inside a data register is provided. The current-limiting circuitry controls a...
US-7,916,514 Shunted phase change memory
By using a resistive film as a shunt, the snapback exhibited when transitioning from the reset state or amorphous phase of a phase change material, may be...
US-7,916,150 Methods, systems, and data structures for generating a rasterizer
Methods, systems and data structures produce a rasterizer. A graphical state is detected on a machine architecture. The graphical state is used for assembling a...
US-7,915,694 Gate electrode having a capping layer
A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer...
US-7,915,642 Apparatus and methods for forming a modulation doped non-planar transistor
Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors...
US-7,915,171 Double patterning techniques and structures
Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor...
US-7,915,167 Fabrication of channel wraparound gate structure for field-effect transistor
A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the...
US-7,915,081 Flexible interconnect pattern on semiconductor package
An embodiment of the present invention is a technique to fabricate a metal interconnect. A first metal trace is printed on a die attached to a substrate or a...
US-7,915,060 Grid array connection device and method
A method and device for input/output connections is provided. Devices and methods for connection structure are shown with improved mechanical properties such as...
US-7,914,740 Biosensor utilizing a resonator having a functionalized surface
Systems and methods for detecting the presence of biomolecules in a sample using biosensors that incorporate resonators which have functionalized surfaces for...
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