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Technique for implementing a security algorithm
Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the...
Beam-former and combiner for a multiple-antenna system
A compensating correction value for adjusting analog signals received from multiple antenna elements takes into account the effects of colored noise, co-channel...
Base station and method for allocating bandwidth in a broadband wireless
network with reduced latency
Systems and methods for allocating bandwidth in a wireless network are generally described herein. Bandwidth is allocated to a mobile station during an...
Ordered and duplicate-free delivery of wireless data frames
Methods and apparatus for delivering ordered and duplicate-free wireless data frames are generally described and claimed herein. Other embodiments may also be...
Maskable content addressable memory
A maskable content addressable memory may store one or more address prefixes. A port on which the packet may be sent is determined by comparing the destination...
Method, apparatus and system for optimizing packet throughput for content
processing systems on chips
An apparatus and system provide an optimizing content processing throughput for systems on chips ("SoCs"). A Packet Processing Memory Controller Cache ("PPMCC")...
Jitter buffer management in a packet-based network
A method, system and computer program product for handling a session in a packed-based network is provided. The method involves the transmission of packets...
Methods and arrangements for selection of a wireless transmission method
based upon signal to noise ratios
Methods and arrangements for wireless communications are contemplated. Embodiments include transformations, code, state machines or other logic to determine the...
Dynamic multi-access relaying for wireless networks
Methods, apparatuses and systems for communicating in a wireless network are disclosed. One embodiment includes a method for communication in a wireless network...
Wake on wireless network techniques
Wake on wireless network techniques are described. An apparatus may include a wireless transceiver, a processor coupled to said transceiver, and a connection...
Method, system, and apparatus for loopback parameter exchange
A loopback test to test a communication link for a layered interface where in a master agent programs the electrical parameters for the slave agent, such as, the...
Resource based data rate control
A method implemented in a node to forward data packets via a communication link to another node. The method includes receiving an indication of a resource level...
Molecular quantum memory
Apparatus, systems and methods for implementing molecular quantum memory are disclosed. In one implementation, a source of polarized electrons and a source of...
Disclosed herein is a wake-up circuit for a bias input of a circuit such as a slave DLL circuit, to allow it to be placed in a reduced power mode and be "awoken"...
Forming ultra dense 3-D interconnect structures
Methods of forming a microelectronic structure are described. Embodiments of those methods include bonding at least one bond pad of a device side of a first...
Compliant integrated circuit package substrate
An integrated circuit package may include a plurality of interconnects, and an integrated package substrate coupled to the plurality of interconnects and...
Stress absorption layer and cylinder solder joint method and apparatus
An apparatus, method, and system for providing a stress absorption layer for integrated circuits includes a stiffening layer adapted to limit flexing. A...
Tri-gate patterning using dual layer gate stack
In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is...
Solder foams, nano-porous solders, foamed-solder bumps in chip packages,
methods of assembling same, and...
A foamed solder or a nano-porous solder is formed on a substrate of an integrated circuit package. The foamed solder exhibits a low modulus that resists cracking...
Methods and device for biomolecule characterization
The methods and apparatus 100, disclosed herein are of use for sequencing 150 and/or identifying 160 proteins 230, 310, polypeptides 230, 310 or peptides 230,...
Dielectric film with low coefficient of thermal expansion (CTE) using
liquid crystalline resin
An embodiment of the present invention is a technique to provide a dielectric film material with a controllable coefficient of thermal expansion (CTE). A first...
Computer system identification
A computer system includes an interface and a processor. The interface is adapted to receive a request from another computer system for identification of the...
Security protocols on incompatible transports
"Honest" is a nice word. Sadly, some people in this world are not honest. In an increasingly wired world, dishonest people have found myriad opportunities to...
Accelerating integrity checks of code and data stored in non-volatile
In some embodiments, a command may be used by a host processor to access certain information from a non-volatile memory, together with a message authentication...
Processor having a dedicated hash unit integrated within
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a...
Sequencer address management
Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or...
Interrupt mailbox in host memory
Embodiments of an interrupt mailbox in host memory are described herein. In an implementation, a device connected to a host writes interrupt data corresponding...
Driver transparent message signaled interrupts
Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message...
Quality of service (QoS) processing of data packets
The present disclosure provides a method for providing Quality of Service (QoS) processing of a plurality of data packets stored in a first memory. The method...
Method and system for dynamic application layer gateways
A method and system are disclosed for providing functionality on a network. A mobile agent moves from a first node to a target node and, at the target node,...
Mechanism for estimating and controlling di/dt-induced power supply
A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response...
Filter scheme for receiver
Provided are a method, system, and device directed to a receive path for a node in a communication system such as a Radio Frequency Identification (RFID) system....
Piezo fans for cooling an electronic device
A cooling system including one or more piezo fans for an electronic assembly is disclosed. The electronic assembly may include heat-generating components coupled...
Image adaptation phase-in
Embodiments of the present invention can phase in image adaptations for display devices by determining a next incremental step among a plurality of incremental...
MOSFET gate interface
In some embodiments a power circuit includes a driver output, a MOSFET, and circuitry to ensure a full and fast positive drive to a gate of the MOSFET when the...
Inverted planar avalanche photodiode
An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a semiconductor substrate layer including a first...
Highly-selective metal etchants
A highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is described. In one...
Method for manufacturing a semiconductor device using the self aligned
contact (SAC) process flow for...
In one embodiment, a method, comprises forming a diffusion layer on a semiconductor substrate, forming a selectively deposited metal or metal alloy on an...
Method of manufacturing semiconducting device with stacked dice
Some embodiments of the present invention relate to a semiconducting device and method that include a substrate and a first die that is attached to the...
Socket enabled current delivery to a thermoelectric cooler to cool an
in-substrate voltage regulator
An apparatus including a socket having a socket body and a cavity within the socket body. The apparatus further including a thermoelectric cooler coupled to an...
Techniques for authenticated posture reporting and associated enforcement
of network access
Architectures and techniques that allow a firmware agent to operate as a tamper-resistant agent on a host platform that may be used as a trusted policy...
Virtual direct memory access crossover
The present disclosure relates to the resource management of virtual machine(s) using information regarding the activity of the virtual machine(s), and, more...
Methods and apparatus to analyze processor systems
Methods and apparatus are disclosed to analyze processor system. An example method to analyze execution of a multi-threaded program on a processor system...
Method, apparatus and system for enhanced CPU frequency governers
A method, apparatus and system enable enhanced processor frequency governors to comprehend virtualized platforms and utilize predictive information to enhance...
System and method to enable processor management policy in a
In some embodiments, the invention involves off-loading processor workloads to reduce power requirements of a multi-processor system. In one embodiment, a...
Method of obscuring cryptographic computations
Obscuring cryptographic computations may be accomplished by performing modular exponentiation of an exponent in a cryptographic computation such that memory...
Hardware-based authentication of a software program
Identity of software is authenticated with hardware on a system. The hardware may be accessible to the operating system, making the mechanisms available to...
Method and apparatus for increasing load bandwidth
A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with...
Method and apparatus for supporting immutable memory
A method for managing a memory in a computer system is disclosed. A mapping of a virtual page to physical page is locked in response to receiving a request to...
Method and apparatus for parallel table lookup using SIMD instructions
Method, apparatus, and program means for performing a parallel table lookup using SIMD instructions. The method of one embodiment comprises loading a table...