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Patent # Description
US-7,879,675 Field effect transistor with metal source/drain regions
A semiconductor device comprising a gate electrode formed on a gate dielectric layer formed on a semiconductor film. A pair of source/drain regions are formed...
US-7,878,016 Device and method for on-die temperature measurement
A system for measuring and managing thermal operations of a processor core on a semiconductor die using a sensor positioned in a hotspot of the processor core. A...
US-7,877,666 Tracking health of integrated circuit structures
Methods and apparatus to track the health of integrated circuit structures are described. In an embodiment, a counter may be updated when the status of a portion...
US-7,877,589 Configuring a device for operation on a computing platform
A method which includes initializing a device following a power cycle. The initialization includes an agent for the device implementing one or more command...
US-7,877,583 Method and apparatus for assigning thread priority in a processor or the like
In a multi-threaded processor, thread priority variables are set up in memory. The actual assignment of thread priority is based on the expiration of a thread...
US-7,877,519 Selecting one of a plurality of adapters to use to transmit a packet
Provided are a method, system, and program for selecting one of a plurality of adapters to use to transmit a packet. A packet is generated by a protocol driver...
US-7,877,504 Techniques for entry lookups
Techniques to store entries so that minimal sequential memory accesses are used to determine all relevant entries. Entries may be grouped into blocks. The order...
US-7,877,339 Method and system of creating an approximate kernel matrix to train a kernel machine
A method and system of creating an approximate kernel matrix to train a kernel machine. In one embodiment of the invention, a set of kernel machine training data...
US-7,877,099 Computing system with off-load processing for networking related tasks
A method is described that comprises executing a service selection method on an off load processor of a computing system to select an available network service...
US-7,876,839 Receiver and method for channel estimation for multicarrier communication systems
Embodiments of system and method for generating channel estimates in a wireless network are generally described herein. Other embodiments may be described and...
US-7,876,765 Method for supporting IP network interconnectivity between partitions in a virtualized environment
A method for preventing loopback of data packets sent between entities residing on a single host. In one embodiment, an auxiliary address shared among entities...
US-7,876,313 Graphics controller, display controller and method for compensating for low response time in displays
Embodiments of a graphics controller, display controller and method for compensating for low-response-time (LRT) displays are generally described herein. Other...
US-7,875,973 Package substrate including surface mount component mounted on a peripheral surface thereof and microelectronic...
A microelectronic combination and a method of making the combination. The combination includes a package substrate including a substrate body having a peripheral...
US-7,875,937 Semiconductor device with a high-k gate dielectric and a metal gate electrode
A semiconductor device is described. That semiconductor device comprises a high-k gate dielectric layer that is formed on a substrate that applies strain to the...
US-7,875,934 Semiconductor substrate with islands of diamond and resulting devices
Disclosed is a method of forming a substrate having islands of diamond (or other material, such as diamond-like carbon), as well as integrated circuit devices...
US-7,875,932 Semiconductor on insulator apparatus
A method and apparatus for producing a relatively thin, relatively uniform semiconductor layer which has improved carrier mobility. In an embodiment, a...
US-7,875,519 Metal gate structure and method of manufacturing same
A method of manufacturing a metal gate structure includes providing a substrate (110) having formed thereon a gate dielectric (120), a work function metal (130)...
US-7,875,503 Reducing underfill keep out zone on substrate used in electronic device processing
Electronic devices and methods for fabricating electronic devices are described. One method includes providing a substrate with a die attach area, and forming a...
US-7,875,415 Helical pixilated photoresist
A helical pixilated photoresist includes a photoacid generator, a photoimageable polymer comprising a self-assembly moiety and a solubility switch, the...
US-7,873,943 Inserting stack clearing code in conservative garbage collection
A location to insert stack clearing code into a method to be executed in an execution environment of a computer system is determined. The stack clearing code is...
US-7,873,892 Techniques to perform forward error correction for an electrical backplane
Techniques to perform forward error correction for an electrical backplane are described. An apparatus comprises a physical layer unit having a forward error...
US-7,873,846 Enabling a heterogeneous blade environment
In one embodiment, the present invention includes a method for receiving a request for power-up of a first blade of a chassis, enabling the first blade to...
US-7,873,698 Alert management messaging
Techniques are described for providing alert management messages in a broadcast environment to individual recipients or to identifiable groups of recipients.
US-7,873,522 Measurement of spoken language training, learning and testing
The fluency of a spoken utterance or passage is measure and presented to the speaker and to others. In one embodiment, a method is described that includes...
US-7,873,134 Clock generation system
Disclosed herein are clock generator systems comprising first and second stage PLLs thereby allowing for both lower PLL bandwidth filtering and higher bandwidth...
US-7,873,068 Flexibly integrating endpoint logic into varied platforms
An integrated endpoint having a virtual port coupled between an upstream fabric and an integrated device fabric that includes a multi-function logic to handle...
US-7,872,892 Identifying and accessing individual memory devices in a memory channel
In one embodiment of the invention, a memory integrated circuit is provided including a memory array, a register, and control logic coupled to the register. The...
US-7,872,864 Dual chamber sealed portable computer
In general, in one aspect, the disclosure describes a laptop computer that can allow for enhanced cooling of a passively cooled notebook while maintaining the...
US-7,872,598 Accelerated decompression
Techniques for decompressing a compressed input by determining, according to an ordering of allowable codewords, an offset for a variable length codeword...
US-7,871,916 Transistor gate electrode having conductor material layer
Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a...
US-7,871,569 Biosensor utilizing a resonator having a functionalized surface
Systems and methods for detecting the presence of biomolecules in a sample using biosensors that incorporate resonators which have functionalized surfaces for...
US-7,870,565 Systems and methods for secure host resource management
Systems and methods are described herein to provide for secure host resource management on a computing device. Other embodiments include apparatus and system for...
US-7,870,545 Protecting shared variables in a software transactional memory system
For a variable accessed at least once in a software-based transactional memory system (STM) defined (STM-defined) critical region of a program, modifying an...
US-7,870,382 Auditable and track-able key distribution and installation system and method for wireless networks
An auditable and track-able key distribution and installation method and system for wireless networks. The method includes registering an installation device and...
US-7,870,373 System and method for automatic update of embedded data
A system and method for maintaining computer platform components in an optimal state. The method determines whether a platform includes an out-of-band processor,...
US-7,870,363 Methods and arrangements to remap non-volatile storage
Methods and arrangements for remapping the map between logical space and physical space in non-volatile storage are described. Embodiments include ...
US-7,870,268 Method, system, and program for managing data transmission through a network
Provided are a method, system, and program for managing data transmission from a source to a destination through a network. The destination imposes a window...
US-7,870,081 Parallelization of bayesian network structure learning
A master computing node directs parallel structure learning with intelligent computational task distribution. The master computing node may determine what...
US-7,869,809 Radio resource measurement and estimation
Apparatus and systems, as well as methods and articles, may operate to conduct radio measurement request and response operations between two stations to...
US-7,869,660 Parallel entropy encoding of dependent image blocks
A method of entropy encoding image or video data may include entropy encoding a number of blocks independently and in parallel to generate a number of bit...
US-7,869,334 Seek-scan probe (SSP) memory with sharp probe tips formed at CMOS-compatible temperatures
Embodiments of a process comprising forming one or more micro-electro-mechanical (MEMS) probe on a conductive metal oxide semiconductor (CMOS) wafer, wherein...
US-7,869,228 Power delivery systems and methods with dynamic look-up table
According to some embodiments, information about a power delivery stage is determined for a plurality of operating condition values. The determined information...
US-7,868,897 Apparatus and method for memory address re-mapping of graphics data
A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating...
US-7,868,318 Quantum well field-effect transistors with composite spacer structures, apparatus made therewith, and methods...
A quantum well (QW) layer is provided in a semiconductive device. The QW layer is covered with a composite spacer above QW layer. The composite spacer includes...
US-7,867,891 Dual metal interconnects for improved gap-fill, reliability, and reduced capacitance
Embodiments of apparatus and methods for forming dual metal interconnects are described herein. Other embodiments may be described and claimed.
US-7,867,863 Method for forming self-aligned source and drain contacts using a selectively passivated metal gate
A transistor structure includes a semiconductor substrate with a first surface, a diffusion region at the first surface of the substrate, a sacrificial gate...
US-7,867,843 Gate structures for flash memory and methods of making same
A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and...
US-7,867,787 Forming inductor and transformer structures with magnetic materials using damascene processing for integrated...
Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a first layer of magnetic material and at...
US-7,867,786 Ferroelectric layer with domains stabilized by strain
The present invention describes a method including: providing a substrate; forming an underlying layer over the substrate; heating the substrate; forming a...
US-7,867,687 Methods and compositions for reducing line wide roughness
Embodiments of the invention provide a non-chemically amplified photoresist, which results in reduced line wide roughness (LWR). In accordance with one...
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