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Dynamic packet error management for wireless communications
Methods and apparatuses for dynamic error rate management. A wireless station may receive one or more data transfer parameters from another wireless station...
Connection management mechanism
A host device is disclosed. The host device includes a receive frame and primitive sequence processor and a connection manager to open a connection with a target...
A method and system for a software driver of a graphics controller to work with a display codec. The software driver may be configured to work with different...
Device configuration with RFID
Various embodiments of the invention may use a radio frequency identification (RFID) tag with a writable non-volatile storage element to receive and store...
Wireless charging device with reflected power communication
Disclosed is a wireless charging device for charging electronic devices placed in a docking area of the wireless charging device. The wireless charging device...
Covered devices in a semiconductor package
An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base...
Field effect transistor with narrow bandgap source and drain regions and
method of fabrication
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer...
Unity beta ratio tri-gate transistor static random access memory (SRAM)
In general, in one aspect, a method includes forming N-diffusion and P-diffusion fins in a semiconductor substrate. A P-diffusion gate layer is formed over the...
Methods to manufacture contaminant-gettering materials in the surface of
Methods to manufacture contaminant-gettering materials in the surface of EUV optics are described herein. An optical element is patterned and a ...
Strain-inducing semiconductor regions
A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent...
Method of enabling solder deposition on a substrate and electronic package
An electronic package includes a substrate (110, 310, 510) and a solder resist layer (120, 320, 520) over the substrate. The solder resist layer has a plurality...
Method for using an in package power supply to supply power to an
integrated circuit and to a component
A packaged device may be provided with an in package power supply. The in package power supply may be selectively coupled to another component when the packaged...
Method of ensuring the integrity of TLB entries after changing the
translation mode of a virtualized operating...
Systems and methods are disclosed to support partial physical addressing modes on a virtual machine. An example method disclosed herein identifies a change of a...
Techniques for decoding information from signals received over multiple
Techniques are described herein that can be used to decode signals received over multiple channels. The received signals may be processed using noise reducing...
Method and apparatus for thermal sensitivity based dynamic power control
A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the...
Method and apparatus for secure execution using a secure memory partition
A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor...
Quiescing a manageability engine
Embodiments of the invention are generally directed to a methods, apparatuses, and systems for quiescing a processor bus agent. In one embodiment, a processor...
Extended trusted computing base
A method, apparatus, and system are provided for extending a trusted computing base (TCB). According to one embodiment, a first level trusted computing base...
Platform management processor assisted resume
In some embodiments, the invention involves system and method for resuming from sleep mode using protected storage accessible to an embedded controller. The boot...
Two-hop cache coherency protocol
The invention facilitates a distributed cache coherency conflict resolution in a multi-node system to resolve conflicts at a home node.
Methods and apparatuses for serial bus sideband communications
Methods and apparatuses that utilize a serial bus, such as a universal serial bus (USB), for communications between a communications network, a computing device,...
Apparatus and method for enumeration of processors during hot-plug of a
An apparatus and method for enumeration of processors during hot-plug of a compute node are described. The method includes the enumeration, in response to a...
Method and apparatus for flash memory reclaim
Machine-readable media, methods, apparatus and system for flash memory reclaim are described. In some embodiment, a system may comprise a flash memory having a...
Method and apparatus for operating a communication station
A method for operating a communication station in a communicating environment includes: (a) monitoring the environment to ascertain whether the station is...
Power saving in VoIP transmission apparatus, systems, and methods
An apparatus, includes a wireless communication module (WCM) to communicatively couple to a wireless access point; and an automatic power-save delivery (APSD)...
Device, system, and method of phased-array calibration
Device, system, and method of phased-array calibration. In some demonstrative embodiments, a wireless communication device may include an array of antenna...
MIMO transmitter and method for transmitting an OFDM symbol in accordance
with an IEEE 802.11 communication...
A multiple-input-multiple output (MIMO) transmitter for transmitting an orthogonal frequency division multiplexed (OFDM) symbol over a plurality of spatial...
Multiple antenna multicarrier transmitter and method for adaptive
beamforming with transmit-power normalization
In a multi-antenna, multicarrier transmitter, a multicarrier communication signal is generated by normalizing beamforming matrices based on an average subcarrier...
Dynamic address redemption by proxy in statically addressed wireless
personal area networks
Described herein are one or more implementations for a mesh, peer-to-peer, cluster-tree, hierarchical wireless personal area network (WPAN) technology that uses...
Techniques to store and access information using a holographic medium
Techniques are described that can be used to store information onto a holographic storage medium. Techniques are described that can be used to access information...
Voltage regulator and method of calibrating the same
A voltage regulator is provided that includes a power cell to provide a calibrated output voltage based on a voltage identification (VID) offset, and a master...
Substrate including barrier solder bumps to control underfill
transgression and microelectronic package...
A microelectronic substrate and a microelectronic package including the substrate and a die bonded thereto. The substrate includes a substrate panel having a...
Heat sink with preattached thermal interface material and method of making
A process of making an integrated heat spreader is disclosed. The integrated heat spreader is stamped with a thermal interface material under conditions to form...
Patterned backside stress engineering for transistor performance
Some embodiments of the present invention include selectively inducing back side stress opposite transistor regions to optimize transistor performance.
Silicon germanium and germanium multigate and nanowire structures for
logic and multilevel memory applications
A method to provide a transistor or memory cell structure. The method comprises: providing a substrate including a lower Si substrate and an insulating layer on...
Apparatus, system, and method for multiple-segment floating gate
Various embodiments include a substrate and a memory cell coupled to the substrate. The memory cell may include an L-shaped floating gate, a control gate, an...
Transistor with improved tip profile and method of manufacture thereof
Embodiments are an improved transistor structure and the method of fabricating the structure. In particular, a wet etch of an embodiment forms source and drain...
Negative tone double patterning method
A method of forming a pattern on a wafer is provided. The method includes applying a photoresist on the wafer and exposing the wafer to define a first pattern on...
Nonplanar semiconductor device with partially or fully wrapped around gate
electrode and methods of fabrication
A nonplanar semiconductor device and its method of fabrication is described. The nonplanar semiconductor device includes a semiconductor body having a top...
Spacer patterned augmentation of tri-gate transistor gate length
In general, in one aspect, a method includes forming a semiconductor substrate having N-diffusion and P-diffusion regions. A gate stack is formed over the...
Programmable electromagnetic array for molecule transport
An embodiment of the invention relates to a device comprising (1) an array of electromagnetic elements comprising coils, metal cores, and metal core heads, and...
Integrated circuit device mounting with folded substrate and interposer
In one embodiment, a package-to-package stack is assembled comprising a first integrated circuit package, and a second integrated circuit package which are...
Processor mode for limiting the operation of guest software running on a
virtual machine supported by a virtual...
In one embodiment, a processor mode is provided for guest software. The processor mode enables the guest software to operate at a privilege level intended by the...
Apparatus and method for redundant software thread computation
An apparatus and method for redundant transient fault detection. In one embodiment, the method includes the replication of an application into two communicating...
Hierarchical test response compaction for a plurality of logic blocks
In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor...
Method and apparatus of power management of processor
Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance...
Method, system, and apparatus for dynamic clock adjustment
A method, apparatus, article of manufacture, and system, the method including, in some embodiments, determining an impedance of a power distribution network of a...
Power efficient resource allocation in data centers
A data center may be operated to achieve reduced power consumption by matching workloads to specific platforms. Attributes of the platforms may be compiled and...
System information synchronization in a links-based multi-processor system
Various embodiments described herein include one or more of systems, methods, firmware, and software to synchronize system information between processors during...
Method and apparatus for changing a configuration of a computing system
Machine-readable media, methods, apparatus and system for caption detection are described. In some embodiments, during a non-quiesce state of a system, a...