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Patent # Description
US-8,031,605 System and method for node-clustering and multi-hop routing in wideband wireless ad-hoc networks
An ad-hoc network system for computing a proposed number of node-clusters that enable a relative threshold data rate. The ad-hoc network system includes a...
US-8,031,267 Motion adaptive upsampling of chroma video signals
Upsampling for video signals is described. In particular chroma pixels may be upsampled in a luminance, chrominance signal using motion adaptive approaches. In...
US-8,031,262 Determining a final exposure setting automatically for a solid state camera without a separate light metering...
An embodiment of the invention is a method of generating a final exposure setting, including, (a) selecting one of a number of predetermined exposure settings...
US-8,031,017 Method and apparatus for determining within-die and across-die variation of analog circuits
Described herein is the method and apparatus for determining frequency of an oscillator coupled with one or more analog devices, and for determining within-die...
US-8,030,968 Staged predriver for high speed differential transmitter
According to various embodiments, a differential transmitter includes a driver and a predriver. In various embodiments, the predriver may include pull-up...
US-8,030,782 Metal-metal bonding of compliant interconnect
Embodiments of the invention provide a first component with a compliant interconnect bonded to a second component with a land pad by a metal to metal bond. In...
US-8,030,757 Forming a semiconductor package including a thermal interface material
In one embodiment, the present invention includes a method for placing a thermal interface material (TIM) between a die including a backside metallic (BSM)...
US-8,030,197 Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow
Embodiments of the invention relate to a method of fabricating logic transistors using replacement metal gate (RMG) logic flow with modified process to form...
US-8,030,163 Reducing external resistance of a multi-gate device using spacer processing techniques
A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to...
US-8,029,922 Forming electroplated inductor structures for integrated circuits
Methods and associated structures of forming microelectronic devices are described. Those methods may include forming a magnetic material on a substrate,...
US-8,029,320 Integrated module including physical layer network device, receptacle and physical layer isolation module
An embodiment may include an integrated module that may include a physical layer network device and a cable connector receptacle. The physical layer network...
US-8,028,341 Providing extended memory protection
In one embodiment, the present invention provides for extended memory protection for memory of a system. The embodiment includes a method for associating a...
US-8,028,295 Apparatus, system, and method for persistent user-level thread
Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and...
US-8,028,282 System for atomically updating a plurality of files
A method for updating platform firmware is disclosed. This capability is facilitated by a standard software abstraction for a firmware storage device, known as...
US-8,028,209 Scalable scan system for system-on-chip design
A method and system to facilitate a scalable scan system in the design of a system-on-chip. In one embodiment of the invention, the system-on-chip includes a...
US-8,028,181 Processor power consumption control and voltage drop via micro-architectural bandwidth throttling
A method, device, and system are disclosed. In one embodiment the method includes supplying a processor with a first voltage. The method also includes allowing...
US-8,028,131 System and method for aggregating core-cache clusters in order to produce multi-core processors
According to one embodiment of the invention, a processor comprises a memory, a plurality of processor cores in communication with the cache memory and a...
US-8,028,129 Dynamically re-classifying data in a shared cache
In one embodiment, the present invention includes a method for determining if a state of data is indicative of a first class of data, re-classifying the data...
US-8,027,702 Combined omni- and directional- communications in high-frequency wireless networks
In a wireless communication network, specific portions of the communication may combine directional transmission with omnidirectional reception. In particular,...
US-8,027,358 Dynamic link width modulation
Techniques for dynamically adjusting point-to-point link width based, at least in part, on link conditions. When operating at full power and at the highest...
US-8,027,186 Programming a phase change memory
A programming circuit of a phase change memory cell includes a controllable current generator to supply a programming pulse and an internal control unit coupled...
US-8,026,879 Energy sensing light emitting diode display
A display that includes energy sensors within the display itself is disclosed. An Organic Light Emitting Diode (OLED) can be made to operate both as a light...
US-8,026,736 Water-level charged device model for electrostatic discharge test methods, and apparatus using same
A charged device model (CDM) electrostatic discharge (ESD) testing is carried out at wafer level. Wafer CDM pulses are repeatedly applied and monitored. The...
US-8,026,706 Adaptive controller with mode tracking and parametric estimation for digital power converters
A controller for a power stage may adaptively control power switches to improve the efficiency of power consumption by the power stage and detect continuous...
US-8,026,509 Tunnel field effect transistor and method of manufacturing same
A TFET includes a source region (110, 210), a drain region (120, 220), a channel region (130, 230) between the source region and the drain region, and a gate...
US-8,025,811 Composition for etching a metal hard mask material in semiconductor processing
An etching solution for a metal hard mask. The etching solution comprises a mixture of a dilute HF (hydrofluoric acid) and a silicon containing precursor. The...
US-8,025,531 Shielded socket housing
A shielded socket and method of fabrication is described. In an embodiment, a socket is formed of a conductive polymer socket housing, and at least one...
US-8,024,806 Method, apparatus and system for enabling a secure location-aware platform
A method, apparatus and system enable a secure location-aware platform. Specifically, embodiments of the present invention may utilize a secure processing...
US-8,024,797 Method, apparatus and system for performing access control and intrusion detection on encrypted data
A method, apparatus and system enable access control and intrusion detection on encrypted data. Specifically, application data on a node may be routed to a...
US-8,024,735 Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution
A system and method for determine which threads to execute at a given time in a multi-threaded computer system. A thread prioritizer determines execution...
US-8,024,730 Switching between protected mode environments utilizing virtual machine functionality
Disclosed is a processor having a normal execution mode and a host execution mode. A virtual machine monitor (VMM) operable in conjunction with the host...
US-8,024,715 Method and apparatus for detecting transient faults via dynamic binary translation
A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate...
US-8,024,594 Method and apparatus for reducing power consumption in multi-channel memory controller systems
Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory...
US-8,024,590 Predicting future power level states for processor cores
In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor package to a...
US-8,024,575 System and method for creation and use of strong passwords
The system and method uses user generated questions and answers of multiple levels for added protection from adversaries. There are a first set of question(s)...
US-8,024,477 System and method to establish a peer-to-peer IT backbone
A peer-to-peer IT (Information Technology) backbone. The system includes at least one IT server and a plurality of client computers arranged in a peer-to-peer...
US-8,023,827 Bi-directional parallel optical link
A system is disclosed. The system includes a first optical transceiver having a first set of transmitters and a first set of receivers and a second optical...
US-8,023,757 Fingerprinting digital video for rights management in networks
Systems and methods generate video fingerprints for video data streams. A collection of sub-fingerprints constitute a fingerprint block. The size and temporal...
US-8,023,574 Method and apparatus to support scalability in a multicarrier network
A multicarrier communication device can vary the number of subcarriers being used to carry on multicarrier communication within a network, based on a...
US-8,023,522 Enabling long-term communication idleness for energy efficiency
A network adapter comprises a controller to change to a first mode from a second mode based on a number of transmit packets, sizes of received packets, and...
US-8,022,487 Increasing body dopant uniformity in multi-gate transistor devices
Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device...
US-8,021,940 Methods for fabricating PMOS metal gate structures
Methods of forming a microelectronic structure are described. Those methods may include forming a gate dielectric layer on a substrate, forming a metal gate...
US-8,020,201 Selecting a security format conversion for wired and wireless devices
A selection system and method to receive an indication of a security format from a network and to select one of a plurality of security format conversions based...
US-8,020,158 Installing and executing shared applications in shared folders
Provided are a method, system, and program for installing and executing shared applications in shared folders. A program is installed by a base computer, having...
US-8,020,142 Hardware accelerator
A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to...
US-8,020,056 Memory channel with bit lane fail-over
Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having...
US-8,020,009 Dynamic performance management of network interface
A dynamic power management technique to optimize the performance to a pre-defined power or temperature limit. A computing system may comprise a performance...
US-8,019,972 Digital signal processor having a plurality of independent dedicated processors
A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized...
US-8,019,947 Technique for thread communication and synchronization
A technique for thread synchronization and communication. More particularly, embodiments of the invention pertain to managing communication and synchronization...
US-8,019,939 Detecting data mining processes to increase caching efficiency
Methods and apparatus to detect a data mining process are presented. In one embodiment the method comprising monitoring access of a process to a resource and...
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