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Patent # Description
US-9,013,158 Switched mode power supply and a method for operating a switched mode power supply
A switched mode power supply provides a reduction of switching losses and increased efficiency. The switched mode power supply includes a first switch coupled...
US-9,012,284 Nanowire transistor devices and forming techniques
Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within...
US-9,011,022 Combined optical and electrical interface
A connection port provides electrical and/or optical interface capability. The combined electrical and optical interface port may include an optical...
US-9,010,618 Magnetic attachment structure
The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic...
US-RE45,487 Processor having execution core sections operating at different clock rates
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section...
US-9,009,854 Platform-hardened digital rights management key provisioning
Embodiments of an invention for platform-hardened digital rights management key provisioning are disclosed. In one embodiment, a processor includes an execution...
US-9,009,759 Terminating enhanced television broadcasts
An enhanced television broadcast system may enable the transmission and reception of a real-time event when a new program is about to begin. The real-time event...
US-9,009,689 Speculative compilation to generate advice messages
Methods to improve optimization of compilation are presented. In one embodiment, a method includes identifying one or more optimization speculations with...
US-9,009,688 Type checking for object-oriented programming languages
Type checking between an object class and a target class may comprise getting an object header from an object, and checking from the object header a result of a...
US-9,009,540 Memory subsystem command bus stress testing
A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory...
US-9,009,531 Memory subsystem data bus stress testing
A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a...
US-9,009,483 Replacing blinded authentication authority
A manufacturing entity provides a blinded signature to a secure device and associates a time with the blinded signature. If a signing key is compromised, the...
US-9,009,453 Network storage target boot and network connectivity through a common network device
The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network...
US-9,009,448 Multithreaded DFA architecture for finding rules match by concurrently performing at varying input stream...
Disclosed is an architecture, system and method for performing multi-thread DFA descents on a single input stream. An executer performs DFA transitions from a...
US-9,009,413 Method and apparatus to implement lazy flush in a virtually tagged cache memory
A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update...
US-9,009,367 Adaptive interrupt moderation
Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the...
US-9,009,366 Method and apparatus for minimizing within-die variations in performance parameters of a processor
Described herein are a method and an apparatus for minimizing within-die variations in performance parameters of a processor. The apparatus comprising: a...
US-9,009,362 Variable-width command/address bus
Embodiments of the invention relate to a variable-width command/address bus (CA bus). In one embodiment, a memory controller includes first logic to determine...
US-9,009,263 Method and apparatus for command synchronization
Method and apparatus for command synchronization is described. In some embodiments, a remote system may set up a user interactive session with a local device...
US-9,008,647 Mobile radio communication network device, mobile terminal, and method for transmission/reception of control...
A mobile radio communication network device is described including a receiver configured to receive control information from a mobile terminal, wherein the...
US-9,008,641 Detecting a user-to-wireless device association in a vehicle
A location of a wireless device relative to a vehicle is determined using received data. Data may be received from the vehicle sensors. Data may also be...
US-9,008,581 Radio devices and methods for controlling radio devices
In an embodiment, a radio device is provided. The radio device may include a signal transmitter configured to transmit a plurality of signals, the signals being...
US-9,008,309 Circuit arrangement and a method for roaming between a visited network and a mobile station
According to various aspects of this disclosure, a circuit arrangement is provided. The circuit arrangement may include: a memory configured to store a first...
US-9,008,304 Content protection key management
This disclosure is directed to content protection key management. In general, devices may include secure processing resources configured to derive content keys...
US-9,008,252 Circuit, method and mobile communication device
A circuit includes an oscillator, a variable phase adjuster and a feedback loop. The oscillator is configured to provide an RF signal, wherein the oscillator is...
US-9,008,243 Method and apparatus for correcting a reference clock of a GPS receiver
An approach is provided for correcting a reference clock of a GPS receiver. The approach involves determining one or more frequency offset values. The approach...
US-9,008,237 Method and device for symbol detection
A method for symbol detection includes assigning a received symbol to at least one particular candidate symbol of a set of candidate symbols of a finite...
US-9,008,231 Signal duty cycle reduction
A method may include receiving a positive in-phase ("I")-channel signal ("I+ signal"), a negative I-channel signal ("I- signal"), a positive quadrature-phase...
US-9,008,207 Uplink noise estimation for virtual MIMO
A system and methods for estimating a noise power level in an uplink signal for a virtual MIMO system is disclosed. The system comprises a demodulation...
US-9,008,167 Methods and arrangements for phase tracking for multi-mode operation in wireless networks
Logic may comprise a single phase tracking implementation for all bandwidths of operation and the logic may adaptively change pre-defined and stored track...
US-9,008,059 Inverse multiplexing over 802.11 wireless interfaces
In accordance with various aspects of the disclosure, a method and apparatus are disclosed that includes aspects of providing one or more data packets at a...
US-9,008,058 Techniques for spatial reuse in wireless personal area networks based on virtual time divisional multiple access
An embodiment of the present invention provides a method, comprising configuring a transceiver for special reuse using a virtual time division multiple access...
US-9,008,018 Dynamic point selection via a coordinating set of base stations
Examples are disclosed for coordinating transmission of one or more protocol data units to a wireless device from a coordinating set of base stations. In some...
US-9,007,972 Communication state transitioning control
Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for managing state transitions of...
US-9,007,967 BSS/PBSS support and schedule-free networking in 60GHz
In accordance with various aspects of the disclosure, an apparatus is disclosed that includes a network coordinator module configured to coordinate operation in...
US-9,007,799 Low power content addressable memory system
A content addressable memory (CAM) system includes one or more CAM cells, each including a bit cell to store a bit and a complementary bit, and a compare...
US-9,007,524 Techniques and apparatus for audio isolation in video processing
An apparatus may include a digital display, processor circuit, and an audio isolation component. The audio isolation component may be operative on the processor...
US-9,007,126 Multi-mode amplifier system
A multi-mode amplifier system includes a supply converter and a multi-stage amplifier. The supply converter is configured to generate a plurality of varied...
US-9,006,890 Solder in cavity interconnection structures
The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first...
US-9,006,887 Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a...
US-9,006,707 Forming arsenide-based complementary logic on a single substrate
In one embodiment, the present invention includes a method for forming a logic device, including forming an n-type semiconductor device over a silicon (Si)...
US-9,006,069 Pulsed laser anneal process for transistors with partial melt of a raised source-drain
A non-planar transistor including partially melted raised semiconductor source/drains disposed on opposite ends of a semiconductor fin with the gate stack...
US-9,005,875 Pre-patterned hard mask for ultrafast lithographic imaging
A method of fabricating a substrate including coating a first resist onto a hardmask, exposing regions of the first resist to electromagnetic radiation at a...
US-9,003,642 Method for making a magnetically coupled thin-wafer handling system
The present invention describes a method of and an apparatus for including: separating magnets and corresponding target plates; separating a lower support...
US-9,003,421 Acceleration threads on idle OS-visible thread execution units
Disclosed are embodiments of a system, methods and mechanism for using idle thread units to perform acceleration threads that are transparent to the operating...
US-9,003,375 Optional logging of debug activities in a real time instruction tracing log
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing optional logging...
US-9,003,246 Functional memory array testing with a transaction-level test engine
A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a...
US-9,003,236 System and method for correct execution of software based on baseline and real time information
In an embodiment of the invention an application provider may include "tracing elements" in a target software application. While working with the application...
US-9,003,210 Dynamic voltage transitions
The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an...
US-9,003,209 Efficient integrated switching voltage regulator comprising switches coupled to bridge drivers to provide...
Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power...
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