Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching: intel





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-1,012,2642 Managing a data stream in a multicore system
Techniques are provided for managing the forwarding of a data stream to respective cores of a multi-core system, in which the incoming data stream is processed...
US-1,012,2628 Station (STA), access point (AP) and method for rate adaptation
Embodiments of a station (STA), access point (AP) and method for rate adaption are generally described herein. The STA may receive a medium access control...
US-1,012,2566 Delay span classification for OFDM systems using selective filtering in the frequency domain
It is proposed a method for delay spread classification of an orthogonal frequency-division multiplexing signal (multiplexing signal), and a receiving device...
US-1,012,2565 Downlink resource scheduling
Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for downlink resource scheduling in wireless...
US-1,012,2526 Phase detector in a delay locked loop
Technology for a phase detector is described. The phase detector can include a reference clock. The phase detector can include a feedback clock. The phase...
US-1,012,2522 Methods and devices for synchronizing data reception from a first radio network and from a second radio network
A synchronization device includes a receiver circuit configured to receive data from a first radio network during a first time interval and to receive data from...
US-1,012,2510 Method, apparatus, and computer readable medium for signaling high efficiency packet formats using a legacy...
Methods, apparatuses, and computer readable media for signaling high-efficiency packet formats using a legacy portion of the preamble in wireless local-area...
US-1,012,2509 Reference signal enhancement for shared cell
In embodiments, apparatuses, methods, and storage media may be described for distinguishing, by a user equipment (UE), a reference signal (RS) transmitted by a...
US-1,012,2504 Device, system and method of transferring a wireless communication session between wireless communication...
Some demonstrative embodiments include coordinating a session transfer between first and second multi-band wireless communication devices capable of...
US-1,012,2484 Technologies for internal time syncrhonization
Technologies for internal time synchronization in a compute device are disclosed. A timestamp value from an always running timer in the compute device may be...
US-1,012,2477 Transmitter performance calibration systems and methods
An apparatus is disclosed that includes a transmit chain, a duplexer, a receive chain and a control circuit. The transmit chain is configured to generate a...
US-1,012,2434 Apparatus, system and method of hybrid beamforming training
For example, a first wireless station may be configured to perform hybrid beamforming training including simultaneously communicating a first plurality of...
US-1,012,2420 Wireless in-chip and chip to chip communication
Apparatus and methods are provided for wireless communications between integrated circuits or integrated circuit dies of an electronic system. In an example, an...
US-1,012,2405 Display panel with transparent conductor based isolator and method for improved wireless communications
A communication device includes at least one radio that comprises signal processing circuitry, and at least one antenna coupled to the signal processing...
US-1,012,2347 Adaptive voltage system for aging guard-band reduction
An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a...
US-1,012,2324 Multi-phase amplifier circuits and methods for generating an amplified output signal
A multi-phase amplifier circuit includes an amplification circuit configured to generate a plurality of phase signals and to provide the plurality of phase...
US-1,012,2265 Reducing electromagnetic interference in switching regulators
An apparatus is provided which comprises: at least two switches in series between an input voltage node and a ground terminal; an inductor coupled between a...
US-1,012,2209 Tunable delay control of a power delivery network
An apparatus system is provided which comprises: a first component to receive a first signal via a first delay circuit; a second component to receive a second...
US-1,012,2205 Systems and methods for adaptive charge termination
A system for increasing the life of a battery cell by limiting the charging of the battery to less than full charge in response to a predicted electricity draw...
US-1,012,2204 Techniques for wire-free charging
Various embodiments are generally directed to techniques for wire-free charging. Some embodiments are particularly directed to a wire-free charging system that...
US-1,012,2089 Magnetic nanocomposite materials and passive components formed therewith
A method apparatus and material are described for radio frequency passives and antennas. In one example, an electronic component has a synthesized magnetic...
US-1,012,1897 Field effect transistor with narrow bandgap source and drain regions and method of fabrication
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer...
US-1,012,1882 Gate line plug structures for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated...
US-1,012,1875 Replacement gate structures for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated...
US-1,012,1861 Nanowire transistor fabrication with hardmask layers
A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire...
US-1,012,1856 Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device...
US-1,012,1792 Floating body memory cell having gates favoring different conductivity type regions
A method for fabricating floating body memory cells (FBCs), and the resultant FBCs where gates favoring different conductivity type regions are used is...
US-1,012,1752 Surface finishes for interconnection pads in microelectronic structures
A surface finish may be formed in a microelectronic structure, wherein the surface finish may include a multilayer interlayer structure. Thus, needed...
US-1,012,1730 Package integrated synthetic jet device
Embodiments include a synthetic jet device formed within layers of a package substrate, such as to provide a controlled airflow for sensing or cooling...
US-1,012,1726 Cooler for semiconductor devices
Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source....
US-1,012,1722 Architecture material and process to improve thermal performance of the embedded die package
A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer...
US-1,012,1701 Substrate conductor structure and method
Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods...
US-1,012,1679 Package substrate first-level-interconnect architecture
Embodiments of the present disclosure may relate to a package substrate that may include a layer having a layer surface that is planarized and a via within the...
US-1,012,1532 Apparatus, method and system for performing successive writes to a bank of a dynamic random access memory
Techniques and mechanisms to provide write access to a memory device. In an embodiment, a memory controller sends commands to a memory device which comprises...
US-1,012,1528 Apparatus, method and system for providing termination for multiple chips of an integrated circuit package
Techniques and mechanisms for providing termination for a plurality of chips of a memory device. In an embodiment, a memory device is an integrated circuit (IC)...
US-1,012,1480 Method and apparatus for encoding audio data
A method for processing audio data includes determining a first common scalefactor value for representing quantized audio data in a frame. A second common...
US-1,012,1277 Progressively refined volume ray tracing
A first set of N samples is located along a ray through a volume in connection with a first frame. The first set of N samples is stored. A second set of N...
US-1,012,1264 Clustered palette compression
Color values may be compressed using a palette based encoder. Clusters of color values may be identified and encoded color values within the cluster with...
US-1,012,1258 Posture system for mobile devices
A system and related methods for determining an actual head angle of a mobile device user from an actual orientation of the mobile device and a relative...
US-1,012,1090 Object detection using binary coded images and multi-stage cascade classifiers
Techniques related to object detection using directional filtering are discussed. Such techniques may include determining directional weighted averages for...
US-1,012,0860 Methods and apparatus to identify a count of n-grams appearing in a corpus
Methods, apparatus, systems and articles of manufacture to identify a count of n-grams appearing in a corpus are disclosed herein. An example method includes...
US-1,012,0814 Apparatus and method for lazy translation lookaside buffer (TLB) coherence
An apparatus and method are described for managing TLB coherence. For example, one embodiment of a processor comprises: one or more cores to execute...
US-1,012,0809 Method, apparatus, and system for allocating cache using traffic class
This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic...
US-1,012,0806 Multi-level system memory with near memory scrubbing based on predicted far memory idle time
An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used...
US-1,012,0805 Managing memory for secure enclaves
A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an...
US-1,012,0798 Dynamic FPGA re-configuration using a virtual FPGA controller
Technologies for field-programmable gate array (FPGA) processing include a computing device having a field-programmable gate array (FPGA) and a virtual FPGA...
US-1,012,0781 Techniques for detecting race conditions
Various embodiments are generally directed to detecting race conditions arising from uncoordinated data accesses by different portions of an application routine...
US-1,012,0774 Coherence protocol tables
An agent is provided to include state table storage to hold a set of state tables to represent a plurality of coherence protocol actions, where the set of state...
US-1,012,0751 Techniques to recover data using exclusive OR (XOR) parity information
Examples may include techniques to recover data from a solid state drive (SSD) using exclusive OR (XOR) parity information. Data saved to non-volatile types of...
US-1,012,0749 Extended application of error checking and correction code in memory
ECC (error checking and correction) can be extended to allow an ECC code to correct memory subarray errors. A memory device includes multiple input/output (I/O)...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.