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| Patent # | Description |
|---|---|
| US-9,385,094 |
Apparatus, system, and method for wireless connection in integrated
circuit packages Some embodiments of the invention include a connecting structure between a support and at least one die attached to the support. The die includes a number of... |
| US-9,385,085 |
Interconnects with fully clad lines A metallization layer including a fully clad interconnect and a method of forming a fully clad interconnect. An opening is formed in a dielectric layer, wherein... |
| US-9,385,082 |
Method of forming high density, high shorting margin, and low capacitance
interconnects by alternating recessed... Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to... |
| US-9,385,033 |
Method of forming a metal from a cobalt metal precursor A metal precursor and a method comprising decomposing a metal precursor on an integrated circuit device; and forming a metal from the metal precursor, wherein... |
| US-9,384,995 |
Tungsten salicide gate source for vertical NAND string to control on
current and cell pillar fabrication A non-volatile memory device and a method for forming the non-volatile memory device are disclosed. During fabrication of the memory device, a tungsten salicide... |
| US-9,384,831 |
Cross-point memory single-selection write technique A system and technique is disclosed for writing data in a cross-point memory. The state of one or more memory cells of the cross-point memory are sensed and... |
| US-9,384,821 |
Row hammer monitoring based on stored row hammer threshold value Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data... |
| US-9,384,801 |
Threshold voltage expansion Embodiments including systems, methods, and apparatuses associated with expanding a threshold voltage window of memory cells are described herein. Specifically,... |
| US-9,384,709 |
Techniques, apparatus, system and method for improved display calibration Embodiments of a device, system, method and other techniques are described for improved display calibration. An apparatus for display calibration may comprise,... |
| US-9,384,539 |
Method and device for processing digital image, and computer-readable
recording medium There is provided a method of processing a digital image including: (a) obtaining a plurality of images; (b) converting the plurality of images into histograms;... |
| US-9,384,385 |
Face recognition using gradient based feature analysis Computer-readable storage media, computing devices and methods are discussed herein. In embodiments, a computing device may be configured to perform facial... |
| US-9,384,368 |
Instruction and logic for mid-level caching of random numbers distributed
to multiple units A system including a memory to store a plurality of digital random numbers generated by a digital random number generator, a plurality of cores coupled to the... |
| US-9,384,367 |
Measuring platform components with a single trusted platform module In accordance with some embodiments, a single trusted platform module per platform may be used to handle conventional trusted platform tasks as well as those... |
| US-9,384,352 |
Trusted boot and runtime operation An embodiment includes an apparatus comprising: an out-of-band cryptoprocessor including secure non-volatile storage that couples to a root index, having a... |
| US-9,384,351 |
Method and apparatus for implementing a secure boot using multiple
firmware sources Technologies for implementing a secure boot using multiple firmware sources are described. One or more fuses of a processing device can be configured. Based on... |
| US-9,384,331 |
Device, system and method of wirelessly delivering content Some demonstrative embodiments include devices, systems and/or methods of wirelessly delivering content. For example, a method may include receiving at a first... |
| US-9,384,164 |
Mapping memory controller connectors to memory connectors Provided are a device, system, and method for mapping memory controller connectors to memory connectors. A memory is programmed to transmit for each of a... |
| US-9,384,163 |
Non-linear termination for an on-package input/output architecture An on-package interface. A first set of single-ended transmitter circuits on a first die. A first set of single-ended receiver circuits on a second die. The... |
| US-9,384,161 |
Method for data throughput improvement in open core protocol based
interconnection networks using dynamically... Methods and apparatus for facilitating data throughput improvements in interconnect fabrics employing point-to-point links using dynamically selectable routing.... |
| US-9,384,154 |
Method to emulate message signaled interrupts with multiple interrupt
vectors Methods to emulate a message signaled interrupt (MSI) with multiple interrupt vectors are described herein. An embodiment of the invention includes a memory... |
| US-9,384,148 |
Detection of unauthorized memory modification and access using
transactional memory Technologies for detecting unauthorized memory accesses include a computing device having transactional memory support. The computing device executes a code... |
| US-9,384,132 |
Emulated message signaled interrupts in a virtualization environment A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache... |
| US-9,384,076 |
Allocating machine check architecture banks In accordance with embodiments disclosed herein, there is provided systems and methods for allocating machine check architecture banks. The processing device... |
| US-9,384,039 |
Parallel memory migration A method and apparatus is described herein for performing parallel memory migration, as well as execution of management tasks over a plurality of management... |
| US-9,384,037 |
Memory object reference count management with improved scalability Generally, this disclosure provides systems, devices, methods and computer readable media for memory object reference count management with improved scalability... |
| US-9,384,025 |
Traffic and/or workload processing In this embodiment, techniques are provided that may permit operations performed by hardware and software to process one or more (e.g., network traffic-related)... |
| US-9,384,015 |
Techniques for dynamically redirecting device driver operations to user
space Various embodiments are generally directed an apparatus and method for configuring an execution environment in a user space for device driver operations and... |
| US-9,384,010 |
Dynamic core swapping An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a... |
| US-9,384,009 |
Dynamic core swapping An embodiment of the present invention is a technique to dynamically swap processor cores. A first core has a first instruction set. The first core executes a... |
| US-9,383,998 |
MFENCE and LFENCE micro-architectural implementation method and system A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that... |
| US-9,383,997 |
Apparatus, system, and method for persistent user-level thread Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and... |
| US-9,383,966 |
Number squaring computer-implemented method and apparatus Embodiments of the present disclosure describe computer-implemented methods, computer-readable media and computer system associated with big number squaring. A... |
| US-9,383,932 |
Data coherency model and protocol at cluster level An apparatus for providing data coherency is described herein. The apparatus includes a global persistent memory. The global persistent memory is accessed using... |
| US-9,383,813 |
Dynamic control of reduced voltage state of graphics controller component
of memory controller A method includes detecting a trigger condition, and in response to detecting the trigger condition, reducing a voltage applied to a graphics controller... |
| US-9,383,812 |
Method and apparatus for efficient store/restore of state information
during a power state A processor is described having streamlining circuitry that has a first interface to receive information from a memory describing: i) respective addresses for... |
| US-9,383,803 |
Priority based application event control (PAEC) to reduce power
consumption Methods and apparatus relating to Priority Based Application Event Control (PAEC) to reduce application events are described. In one embodiment, PAEC may... |
| US-9,383,798 |
Platform and processor power management The present invention relates to platform power management. |
| US-9,383,790 |
Internal communication interconnect scalability Interconnect frequency control technologies of adjusting an operating frequency of a communication interconnect between an integrated circuit comprising... |
| US-9,383,517 |
Alternate coupling of devices via multiple branches of a waveguide Embodiments of the present disclosure are directed toward techniques and configurations for alternate connection of two devices via multiple branches of a... |
| US-9,380,855 |
System and method for generating and using a wearable device profile A system and method for generating and using a wearable device profile are disclosed. A particular embodiment includes: a retention mechanism including an... |
| US-D760,713 |
Tablet computer |
| US-D760,712 |
Curved laptop and tablet device |
| US-9,380,641 |
Mobile station and method for processing signals of the GSM and TD-SCDMA
radio standards A mobile station is disclosed for processing differing radio standards such as GSM/GPRS/EDGE and TD-SCDMA. The mobile station includes a channel decoding unit... |
| US-9,380,634 |
Apparatus, system and method of tearing down a protocol adaptation layer
(PAL) session Some demonstrative embodiments include apparatuses, systems and/or methods of tearing down a Protocol Adaptation Layer (PAL) session. For example, an apparatus... |
| US-9,380,629 |
Message generating arrangement A message generating arrangement determines whether a first communication terminal of a communication system can participate, by means of packet-switching... |
| US-9,380,625 |
Communication terminal device, communication device, communication network
server and method for controlling In various aspects of this disclosure, a communication terminal device may be provided. The communication terminal device may include a cellular wide area radio... |
| US-9,380,494 |
Systems, methods and devices for traffic offloading Wireless communication traffic can be offloaded from a user equipment (UE) to two wireless points of access. For example, user equipment (UE) is connected to a... |
| US-9,380,492 |
Methods, systems and apparatuses to enable short frames Generally, embodiments to enable short frames are described herein. Embodiments may comprise logic such as hardware and/or code to reduce the size of a packet... |
| US-9,380,471 |
Method, apparatus and system of determining a time of arrival of a
wireless communication signal Some demonstrative embodiments include devices, systems and methods of determining a Time of Arrival (ToA) of a wireless communication signal. For example, a... |
| US-9,380,470 |
Determining a receiving quality in a radio communication device A radio communication device including a receiver configured to receive radio signals, a measurement circuit configured to measure the receiving quality of... |
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