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Patent # Description
US-7,999,351 Phase memorization for low leakage dielectric films
Embodiments of a phase-stable amorphous high-.kappa. dielectric layer in a device and methods for forming the phase-stable amorphous high-.kappa. dielectric...
US-7,999,298 Embedded memory cell and method of manufacturing same
An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the...
US-7,999,042 Low coefficient of thermal expansion (CTE) thermosetting resins for integrated circuit applications
An embodiment of the present invention is a technique to form a resin. A mixture is formed by a curing agent dissolved in the epoxy resin. The epoxy resin...
US-7,998,857 Integrated circuit and process for fabricating thereof
A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further...
US-7,996,989 Heat dissipating device with preselected designed interface for thermal interface materials
Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is...
US-7,996,872 Method and apparatus for switching program streams using a variable speed program stream buffer coupled to a...
Various embodiments for switching programs streams using a variable speed program stream buffer coupled to a variable speed decoder are described. In one or...
US-7,996,791 Streaming video programming guide system selecting video files from multiple websites and automatically...
A programming guide for streaming video files may be automatically compiled in response to a user request. The user may provide keywords for categories of...
US-7,996,721 Method and system for a process monitor using a hardware communication format
A method and system for a process monitor using a hardware communication format is described. The system includes a process monitor and a hardware device to...
US-7,996,663 Saving and restoring architectural state for processor cores
A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing...
US-7,996,656 Attaching and virtualizing reconfigurable logic units to a processor
In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and...
US-7,996,644 Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache
An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A...
US-7,996,625 Method and apparatus for reducing memory latency in a cache coherent multi-node architecture
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a...
US-7,996,619 K-way direct mapped cache
A method and apparatus for a k-way direct mapped cache organization is herein described. Control logic coupled to a cache may associate an address to a way...
US-7,996,617 Multithreaded clustered microarchitecture with dynamic back-end assignment
A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and...
US-7,996,572 Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to...
US-7,996,548 Message communication techniques
A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a...
US-7,996,510 Virtual clustering for scalable network control and management
In some embodiments, the invention involves a system and method relating to a framework to build a new class of network control (policy) and (state) management...
US-7,996,049 Remote unit for providing spatial processing
Methods and apparatus implementing spatial processing in a remote unit. In general, in one aspect, a remote unit in accordance with the invention includes a...
US-7,995,662 CQI reporting techniques for OFDMA wireless networks
Various embodiments of the invention may use bitmaps to communicate channel quality index (CQI) information for multiple sub-channels in an orthogonal frequency...
US-7,995,546 Method and system of secured direct link set-up (DLS) for wireless networks
Method and system of secured direct link set-up (DLS) for wireless networks. In accordance with aspects of the method, techniques are disclosed for setting up...
US-7,995,471 High-performance WiMAX QoS condition scheduling mechanism
Embodiments of a method and apparatus for a high performance worldwide interoperability for microwave access quality of service condition scheduling mechanism...
US-7,995,068 Display refresh
A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided...
US-7,993,525 Device and method for particle complex handling
An embodiment of the invention relates to a device for detecting an analyte in a sample. The device comprises a fluidic network and an integrated circuitry...
US-7,992,151 Methods and apparatuses for core allocations
Apparatuses, systems, and methods to monitor core performance and integrated circuit chip temperatures in order to alternatively partition cores and core...
US-7,992,147 Processor control register virtualization to minimize virtual machine exits
A processor includes a processor control register with a control flag that determines an operating mode of the processor. A pointer to a guest virtual machine...
US-7,992,075 Arrangements for encoding and decoding digital data
A method for encoding data is disclosed. The method can include receiving a first bit segment (K-1 bits) from a bit stream, storing the first bit segment,...
US-7,992,039 Failover and load balancing
Provided are techniques for static load balancing implemented in a filter driver. The filter driver determines a data quota for each of multiple data paths. The...
US-7,992,024 Firewall/isolation cells for ultra low power products
In an integrated circuit (IC) may have several functional blocks adapted to be inactivated independently from each other. At least one firewall cell may be...
US-7,992,017 Methods and apparatuses for reducing step loads of processors
Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a...
US-7,991,992 Power reduction for system on chip
Disclosed herein are SOC devices with peripheral units having power management logic.
US-7,991,987 Comparing text strings
A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be...
US-7,991,983 Register set used in multithreaded parallel processor architecture
A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of...
US-7,991,966 Efficient usage of last level caches in a MCMP system using application level configuration
This disclosure presents an architectural mechanism which allows a caching bridge to efficiently store data either inclusively or exclusively based upon...
US-7,991,965 Technique for using memory attributes
A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory...
US-7,991,964 Pre-coherence channel
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the...
US-7,991,963 In-memory, in-page directory cache coherency scheme
In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing...
US-7,991,956 Providing application-level information for use in cache management
In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to...
US-7,991,950 Apparatus and method for incremental package deployment
A method and apparatus for incremental package deployment are described. In one embodiment, the method includes the redirection of disk input/output (I/O)...
US-7,991,875 Link level retry scheme
A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry...
US-7,991,409 Wake-on-WLAN for stationary wireless stations
Stationary wireless network stations are woken up using Wake-on-WLAN functionality. Wake-on-WLAN is provided by paging stations in a wireless network. Paging...
US-7,991,302 Method and apparatus for optical signaling
A method and apparatus for optical signaling. In one embodiment, a laser driver converts a digital voltage sequence to a current signal having a bias mode...
US-7,991,293 Unified optical connector architecture
A system, device, and method are disclosed. In one embodiment the system includes an optical link and a peripheral device optically coupled to the optical link....
US-7,991,252 Blind-mate optical connector for server remote memory application
Blind-made optical connectors may not be robust and tend to be very sensitive to dust. Accordingly, a floating barrel blind mate optical connector is described...
US-7,991,152 Speeding up Galois Counter Mode (GCM) computations
Methods and apparatus to speed up Galois Counter Mode (GCM) computations are described. In one embodiment, a carry-less multiplication instruction may be used...
US-7,991,103 Systems and methods for data recovery in an input circuit receiving digital data at a high rate
Embodiments include systems and methods for recovery of data from an incoming digital data stream. Embodiments comprise a fine tracking loop to track the data...
US-7,991,020 Quad rate transmitter equalization
An integrated circuit includes current mode drivers that provide equalized outputs. A parallel-to-serial converter circuit receives data at less than one fourth...
US-7,990,999 Starvation prevention scheme for a fixed priority PCE-express arbiter with grant counters using arbitration pools
Method and apparatus for arbitrating prioritized cycle streams in a manner that prevents starvation. High priority and low priority arbitration pools are...
US-7,990,983 Modular interconnect structure
Some embodiments of the invention include an interconnect structure to transfer data among a plurality of devices. The interconnect structure includes a...
US-7,990,737 Memory systems with memory chips down and up
In some embodiments, a system includes a memory controller chip, memory chips on a first substrate, and a module connector. A first group of conductors is...
US-7,990,469 Cleaning friendly camera privacy feature
Briefly, in accordance with one or more embodiments, an appliance having a camera and camera window may include a shutter puck slidably disposed in a slot in...
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