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Patent # Description
US-9,699,731 Inter-node interference cancellation
A method for cancelling inter-node interference at a victim node is disclosed, which method may be executed as instructions on a machine, where the instructions...
US-9,699,727 Method, apparatus, and computer readable medium for signaling high efficiency preambles
Methods, apparatuses, and computer readable media are disclosed to signal a packet configuration. A HEW device to signal a packet configuration may include...
US-9,699,324 Framework for unlicensed spectrum usage monitoring and reporting in LTE networks
An unlicensed spectrum usage monitoring and reporting method is disclosed. The unlicensed spectrum usage monitoring and reporting method employs a new logical...
US-9,698,959 Method and apparatus for processing a downlink shared channel
A method and apparatus is disclosed in which a user equipment (UE) receives and processes control information received on a first channel. In accordance with a...
US-9,698,889 Scheduling in a multiple user multiple-input and multiple output communications network
A technology that is operable to schedule data transfer for a multiple user multiple-input and multiple-output (MU-MIMO) communications network is disclosed. In...
US-9,698,838 Real-time blocker-adaptive broadband wireless receiver for low-power operation under co-existence in 5G and beyond
A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein,...
US-9,698,764 Quadrature divider
Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus...
US-9,698,628 System integration of wireless power transmission subsystem
In accordance with various aspects of the disclosure, systems, methods, and devices are disclosed that include a power source integrated with a host computing...
US-9,698,222 Method of fabricating semiconductor structures on dissimilar substrates
Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask...
US-9,698,108 Structures to mitigate contamination on a back side of a semiconductor substrate
Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment, a...
US-9,697,648 Text functions in augmented reality
Various systems and methods for implementing text functions in augmented reality are described herein. A system for implementing text functions in augmented...
US-9,697,059 Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU
A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A...
US-9,696,999 Local closed loop efficiency control using IP metrics
According to one embodiment, a processor includes an instruction decoder to decode instruction and a execution unit to execute instructions, the execution unit...
US-9,696,775 Integrated circuit with on-chip power profiling
Embodiments include apparatuses, methods, and systems for determining a power consumption of a circuit block in an integrated circuit. The integrated circuit...
US-9,693,278 Load balancing schemes for idle mode user equipment
A user equipment device (UE) comprises physical layer circuitry configured to transmit and receive radio frequency electrical signals with one or more nodes of...
US-9,693,173 Generating, broadcasting and receiving system information blocks
Methods and apparatuses for communicating in a wireless network include receiving full and differential System Information Blocks (SIBs) and updating a...
US-9,692,699 Apparatus, system and method of protecting a service identifier
Some demonstrative embodiments include apparatuses, systems and/or methods of securing a service Identifier (ID). For example, a wireless device may include a...
US-9,692,147 Small form factor sockets and connectors
An electronic device connection system includes a first electrical device and a second electrical device. The first electrical device includes a plurality of...
US-9,691,848 Semiconductor devices with germanium-rich active layers and doped transition layers
Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped...
US-9,691,727 Pad-less interconnect for electrical coreless substrate
A microelectronic device includes a laminated mounting substrate including a die side and a land side with a surface finish layer disposed in a recess on the...
US-9,691,716 Techniques for enhancing fracture resistance of interconnects
Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via...
US-9,691,675 Method for forming an electrical device and electrical devices
A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at...
US-9,691,481 Path isolation in a memory device
Embodiments of the present disclosure describe techniques and configurations for word-line path isolation in a phase change memory (PCM) device. In one...
US-9,691,140 Global matching of multiple images
Global matching of pixel data across multiple images. Pixel values of an input image are modified to better match a reference image with a slope thresholded...
US-9,691,123 Instrumentation of graphics instructions
Embodiments of graphics instruction instrumentor ("GII") and a graphics profiler ("GP") are described. The GII may facilitate profiling of execution of graphics...
US-9,691,122 Facilitating dynamic and efficient pre-launch clipping for partially-obscured graphics images on computing devices
A mechanism is described for facilitating dynamic and efficient pre-launch clipping for partially-obscured images on computing devices. A method of embodiments,...
US-9,691,117 External validation of graphics pipelines
Data may be streamed out of a graphics pipeline during run time without preprogramming the stream out. A command stream may be captured, draw commands...
US-9,690,998 Facial spoofing detection in image based biometrics
Systems and techniques for facial spoofing detection in image based biometrics are described herein. A marker may be created for a representation of a face in a...
US-9,690,716 High performance persistent memory for region-centric consistent and atomic updates
A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent...
US-9,690,704 Paging in secure enclaves
Embodiments of an invention for paging in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The...
US-9,690,683 Detection and handling of virtual network appliance failures
In one aspect, a method is implemented on a host platform on which a hypervisor (aka Virtual Machine Manager) and a plurality of virtual machines (VMs) are...
US-9,690,640 Recovery from multiple data errors
Mechanisms for handling multiple data errors that occur simultaneously are provided. A processing device may determine whether multiple data errors occur in...
US-9,690,615 Live migration of virtual machines from/to host computers with graphics processors
Apparatuses, methods and storage medium associated with live migration of virtual machines (VMs) from/to host computers with graphics virtualization are...
US-9,690,503 Returning coherent data in response to a failure of a storage device when a single input/output request spans...
A controller maintains exposed and unexposed locations of a first storage device and a second storage device. In response to receiving a request a perform a...
US-9,690,493 Two-level system main memory
Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main...
US-9,690,340 System and method for adaptive thermal and performance management in electronic devices
A system and method for adaptive thermal and performance management in electronic devices are disclosed. A particular embodiment includes: providing a processor...
US-9,690,092 MEMS scanning mirror light pattern generation
Techniques and configurations for an apparatus for projecting a light pattern on an object are described. In one embodiment, the apparatus may include a laser...
US-9,689,961 Apparatus, system and method of communication between wireless networks having different coordinate domains
Some demonstrative embodiments include apparatuses, systems and/or methods of communication between wireless networks having different coordinate domains. For...
US-9,689,704 Sketch aided route selection for navigation devices and applications
One particular example includes a system, comprising a processor and a memory to store instructions that when executed by the processor performs operations,...
US-9,686,694 Techniques to support directional transmission and reception by wireless network boosters
Techniques to support directional transmission and reception by wireless network boosters are described. In one embodiment, for example, an apparatus may...
US-9,686,460 Enabling a metadata storage subsystem
The present disclosure provides techniques for enabling a metadata storage subsystem. A directory of available metadata is created, and the metadata is stored...
US-9,686,440 Rendering high quality images via micro-segmentation, error diffusion, and edge enhancement
Techniques related to rendering scanned images are discussed. Such techniques may include selectively processing segments of a scanned input image based on a...
US-9,686,089 Scheduling timing design for a TDD system
Disclosed is a method of transmitting, from an enhanced Node B (eNB), an indication of an uplink/downlink (UL-DL) subframe configuration of a scheduling cell...
US-9,686,025 Proximate communication with a target device
Systems and methods may use proximate communication to retrieve information pertaining to a target device. In one example, the method may include detecting the...
US-9,685,508 High voltage field effect transistors
Transistors suitable for high voltage and high frequency operation are disclosed. A nanowire is disposed vertically or horizontally on a substrate. A...
US-9,685,413 Semiconductor package having an EMI shielding layer
Semiconductor packages and methods of forming semiconductor packages are described. In an example, a semiconductor package includes a shielding layer containing...
US-9,685,390 Microelectronic package having non-coplanar, encapsulated microelectronic devices and a bumpless build-up layer
A microelectronic package having an encapsulated substrate comprising a plurality of microelectronic devices encapsulated within an encapsulation material,...
US-9,685,388 Picture frame stiffeners for microelectronic packages
A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An...
US-9,685,381 Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon
Different n- and p-types of device fins are formed by epitaxially growing first epitaxial regions of a first type material from a substrate surface at a bottom...
US-9,684,595 Adaptive hierarchical cache policy in a microprocessor
A method for determining an inclusion policy includes determining a ratio of a capacity of a large cache to a capacity of a core cache in a cache subsystem of a...
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