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Patent # Description
US-9,552,303 Method and system for maintaining release consistency in shared memory programming
A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in...
US-9,552,269 Test logic for a serial interconnect
An apparatus that includes a serial interconnect is provided, wherein the serial interconnect includes test logic to send a number of reporting messages,...
US-9,552,267 SATA receiver equalization margin determination/setting method and apparatus
Apparatuses, methods and storage medium associated with automatic SATA receiver equalization margin determination and setting, are disclosed. In embodiments, an...
US-9,552,253 Probabilistic flit error checking
A bit error in a flit transmitted over a link is determined to affect one or more particular bits of the flit based on a syndrome value associated with a cyclic...
US-9,552,209 Functional unit for instruction execution pipeline capable of shifting different chunks of a packed data...
A method is described that includes fetching an instruction. The method further includes decoding the instruction. The instruction specifies an operation, a...
US-9,552,207 Method and apparatus for performance efficient ISA virtualization using dynamic partial binary translation
Methods, apparatus and systems for virtualization of a native instruction set are disclosed. Embodiments include a processor core executing the native...
US-9,552,205 Vector indexed memory access plus arithmetic and/or logical operation processors, methods, systems, and...
A processor including a decode unit to receive a vector indexed load plus arithmetic and/or logical (A/L) operation plus store instruction. The instruction is...
US-9,552,169 Apparatus and method for efficient memory renaming prediction using virtual registers
A method and apparatus are described for efficient memory renaming prediction using virtual registers. For example, one embodiment of an apparatus comprises: a...
US-9,552,164 Apparatus, method and system for determining reference voltages for a memory
Techniques and mechanisms for a memory device to concurrently receive and process signals each based on a different respective reference voltage level. In an...
US-9,552,159 Configuration information backup in memory systems
According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status...
US-9,552,051 Block partition to minimize power leakage
Disclosed herein is a system to minimize power leakage. The system is configured to include a system-on-chip (SOC). The SOC is configured to include a Universal...
US-9,552,045 Method, apparatus, and system for controlling power consumption of unused hardware of a link interface
In an embodiment, a plurality of hardware buffers each may store information associated with one or more virtual channels. In turn, a configuration logic is to...
US-9,552,039 Constrained boot techniques in multi-core platforms
Methods and apparatus relating to constrained boot techniques in multi-core platforms are described. In one embodiment, a processor may include logic that...
US-9,551,916 Integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing...
A system and method for implementing integrated and adjustable image projection with auto-image correction in electronic devices using an in-facing or...
US-9,551,741 Current tests for I/O interface connectors
Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data...
US-9,551,682 High throughput biochemical detection using single molecule fingerprinting arrays
Various embodiments provide devices, methods, and systems for high throughput biomolecule detection using transducer arrays. In one embodiment, a transducer...
US-9,551,352 Techniques for improved volumetric resistance blower apparatus, system and method
Embodiments of an apparatus, system, method and techniques are described for an improved volumetric resistance blower and rotor. An apparatus may comprise, for...
US-9,551,177 Rotational to translational locking hinge
Techniques related to a hinge in a computing device are described herein. The techniques may include forming a shaft to move rotationally, and forming a sliding...
US-9,550,670 Stress buffer layer for integrated microelectromechanical systems (MEMS)
Stress buffer layers for integrated microelectromechanical systems (MEMS) are described. For example, a semiconductor package includes a substrate having first...
US-9,550,495 Technologies for assisting vehicles with changing road conditions
Technologies for assisting vehicles with changing road conditions includes vehicle assistance data based on crowd-sourced road data received from a plurality of...
US-9,549,421 Network coverage hole detection
A technology for a user equipment (UE) that is operable to connect to a third generation partnership project (3GPP) long term evolution (LTE) cell in a cellular...
US-9,549,404 Blind decoding for an enhanced physical downlink control channel (EPDCCH)
Technology for a user equipment (UE) configured for blind decoding downlink control information (DCI) from an enhanced physical downlink control channel...
US-9,549,378 Power loading in MU-MIMO
Embodiments of a system and method for transmitting data from an access point in a multiple user multiple input multiple output (MU-MIMO) system are provided. A...
US-9,549,286 Geo-fence notification management
Embodiments for geo-fence notification management are generally described herein. A mobile device for geo-fence notification management may include a...
US-9,549,280 Wireless data transfer with improved transport mechanism selection
Generally, this disclosure describes devices, systems and methods for wireless data transfer with improved transport mechanism selection. The device may include...
US-9,549,254 Method and system of acoustic signal mixing
A system, article, and method of acoustic signal mixing comprises use of a total pair that is a count of the number of addition coefficients and subtraction...
US-9,549,188 Golden frame selection in video coding
Techniques related to designating golden frames and to determining frame sizes and/or quantization parameters golden and non-golden frames for video coding are...
US-9,548,986 Sensitive data tracking using dynamic taint analysis
A system and method for tracking sensitive data uses dynamic taint analysis to track sensitive data as the data flows through a target application running on a...
US-9,548,937 Backpressure techniques for multi-stream CAS
Techniques are disclosed for controlling data transmission in multi-stream digital systems. The techniques disclosed allow an input stream to a conditional...
US-9,548,879 Virtual multicarrier design for orthogonal frequency division multiple access communications
Embodiments of the present invention provide a virtual multicarrier design for orthogonal frequency division multiple access communications. Other embodiments...
US-9,548,815 Apparatus for visible light communications in accordance with UFSOOK and FSK dimming
Embodiments may provide a way of communicating via an electromagnetic radiator, or light source, that can be amplitude modulated such as light emitting diode...
US-9,548,750 Circuit, a time-to-digital converter, an integrated circuit, a transmitter, a receiver and a transceiver
A circuit according to an example includes a controllable oscillator configured to generate an output signal based on a control signal, an input signal...
US-9,548,747 Glitch-free digitally controlled oscillator code update
A glitch-free digitally controlled oscillator (DCO) code update may be achieved by synchronizing the transfer of the DCO code update to a logic state transition...
US-9,548,746 Coarse tuning selection for phase locked loops
A phase locked loop system comprises a phase locked loop and an oscillator that is coarse tuned and fine tuned according to coarse tuning operations and fine...
US-9,548,734 Smart impedance matching for high-speed I/O
Embodiments are generally directed to smart impedance matching for high-speed I/O. In some embodiments, a circuit includes an impedance sensing block; a finite...
US-9,548,576 Connector assembly for an electronic device
An electronic device includes an audio jack assembly that is to receive an audio input, wherein the audio jack assembly is provided concentrically with a...
US-9,548,449 Conductive oxide random access memory (CORAM) cell and method of fabricating same
Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory...
US-9,548,441 Perpendicular MTJ stacks with magnetic anisotrophy enhancing layer and crystallization barrier layer
Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy...
US-9,548,410 Photovoltaic window
An apparatus for collecting solar energy, including a first panel, wherein the first panel allows at least 50% of incident light having a wavelength in the...
US-9,548,363 Extreme high mobility CMOS logic
A CMOS device includes a PMOS transistor with a first quantum well structure and an NMOS device with a second quantum well structure. The PMOS and NMOS...
US-9,548,320 Heterogeneous semiconductor material integration techniques
Techniques are disclosed for heteroepitaxial growth of a layer of lattice-mismatched semiconductor material on an initial substrate, and transfer of a...
US-9,548,284 Reduced expansion thermal compression bonding process bond head
Embodiments of a thermal compression bonding process bond head and a method for producing a thermal compression bonding process bond head are disclosed. In some...
US-9,548,269 Diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects
Self-aligned via and plug patterning using diagonal hardmasks for improved overlay in fabricating back end of line (BEOL) interconnects is described. In an...
US-9,548,264 High density organic bridge device and method
Embodiments that allow multi-chip interconnect using organic bridges are described. In some embodiments an organic package substrate has an embedded organic...
US-9,548,137 Integrated circuit defect detection and repair
In accordance with the present description, a device includes an internal defect detection and repair circuit which includes a self-test logic circuit built in...
US-9,547,971 Technologies for determining a threat assessment based on fear responses
Technologies for determining a threat assessment based on fear responses comprises monitoring sensor data received from a sensor array located at a monitored...
US-9,547,918 Techniques for deferred decoupled shading
Various embodiments are generally directed to techniques for reducing the processing demands of shading primitives in rendering a 2D screen image from a 3D...
US-9,547,907 Image segmentation using color and depth information
Image segmentation utilizing 3D image data. A plurality of pixels of an image frame may be segmented based at least on a function of pixel color and a pixel...
US-9,547,880 Parallel processing image data having top-left dependent pixels
Methods and systems may include logic to identify a plurality of blocks in image data having one or more top-left dependent pixels, and select the plurality of...
US-9,547,779 Method and apparatus for secure execution using a secure memory partition
A processor includes a plurality of general purpose registers and cryptographic logic to encrypt and decrypt information. The cryptographic logic is to support...
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