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Patent # Description
US-9,769,290 Packet flow classification
Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table...
US-9,769,169 Secure sensor data transport and processing
The present disclosure is directed to secure sensor data transport and processing. End-to-end security may prevent attackers from altering data during the...
US-9,769,129 Mutually assured data sharing between distrusting parties in a network environment
An apparatus for sharing information between entities includes a processor and a trusted execution module executing on the processor. The trusted execution...
US-9,769,123 Mitigating unauthorized access to data traffic
One particular example implementation of an apparatus for mitigating unauthorized access to data traffic, comprises: an operating system stack to allocate...
US-9,769,106 Displaying notifications on a mobile computing device
Technologies for displaying notifications on a mobile computing device includes determining a notification category for each notification, determining a...
US-9,769,050 End-to-end datacenter performance control
In embodiments, apparatuses, methods and storage media (transitory and non-transitory) are described that are associated with end-to-end datacenter performance...
US-9,768,971 Communication device and a method for operating a communication device
A method and device for reducing the interruption in a first download, i.e. ongoing reception, caused by the start of a second download, i.e. incoming...
US-9,768,951 Symmetric keying and chain of trust
The present disclosure is directed to sealing data using chain of trust key derivation. In at least one embodiment, a chain of trust may be used to derive...
US-9,768,841 Apparatus, system and method of multi-input-multi-output (MIMO) beamformed communication with space block coding
Some demonstrative embodiments include devices, systems and/or methods of beamformed communication with space block coding. For example, an apparatus may...
US-9,768,829 Methods for processing audio signals and circuit arrangements therefor
A method for processing audio signals is provided comprising outputting an audio signal; receiving the output audio signal via a first receiving path as a first...
US-9,768,809 Digital-to-time converter spur reduction
This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an...
US-9,768,802 Look-ahead hash chain matching for data compression
Example data compression methods disclosed herein include determining a first hash chain index corresponding to a first position in an input data buffer based...
US-9,768,788 Phase-locked loop with lower power charge pump
Described is a phase-locked loop with lower power charge pump. The phase-locked loop comprises: a phase frequency detector to compare a reference clock and a...
US-9,768,780 Apparatus for providing shared reference device with metal line formed from metal layer with lower resistivity...
Described is an apparatus which comprises: a reference device; and a processor having a plurality of circuit units, each circuit unit is operable to...
US-9,768,553 Spring connector for electronic devices
In one example an electronic device comprises at least one electronic component, a chassis comprising a first section, a connector to connect the first section...
US-9,768,501 Apparatus, system and method of steering an antenna array
Some demonstrative embodiments include apparatuses, devices systems and/or methods of steering an antenna array. For example, an apparatus may include a...
US-9,768,484 Resonator structure for a cavity filter arrangement
A resonator according to the invention includes an Inner conductor. The resonator has a easing comprising walls, a lid and a bottom shell within which there is...
US-9,768,269 Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth...
US-9,768,249 Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator
Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems...
US-9,768,148 Stacked memory with interface providing offset interconnects
A stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the...
US-9,767,890 Operation aware auto-feedback SRAM
A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a...
US-9,767,858 Register files including distributed capacitor circuit blocks
Some embodiments include apparatuses having a first node to receive a supply voltage, a second node, a switching circuit to couple the first node to the second...
US-9,767,671 System for determining sensor condition
The present disclosure is directed to a system for determining sensor condition. A sensor signal generated by a sensor to communicate the current condition of...
US-9,767,602 Techniques for reduced pixel shading
Various embodiments are generally directed to techniques for reducing processing demands of shading primitives in rendering a 2D screen image from a 3D model. A...
US-9,767,324 Transparent execution of secret content
The present application is directed to transparent execution of secret content. A device may be capable of downloading content that may include at least one...
US-9,767,272 Attack Protection for valid gadget control transfers
In one embodiment, a processor comprises: a first register to store a first bound value for a stack to be stored in a memory; a second register to store a...
US-9,767,235 Method and device for the design of thermal models for electronic systems
The invention relates to a method and device for thermal simulation of electronic systems involving breaking down the system into parts being in a single...
US-9,767,064 Low power universal serial bus
Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer...
US-9,767,044 Secure memory repartitioning
Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and...
US-9,767,042 Enhancing cache performance by utilizing scrubbed state indicators associated with cache entries
Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may...
US-9,767,041 Managing sectored cache
Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to...
US-9,767,038 Systems and methods for accessing a unified translation lookaside buffer
Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one...
US-9,767,037 Technologies for position-independent persistent memory pointers
Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing...
US-9,767,026 Providing snoop filtering associated with a data buffer
In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip...
US-9,767,024 Cache closure and persistent snapshot in dynamic code generating system software
Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation...
US-9,767,020 Systems and methods for faster read after write forwarding using a virtual address
Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from...
US-9,766,999 Monitoring performance of a processing device to manage non-precise events
In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processing device to manage non-precise...
US-9,766,997 Monitoring performance of a processor using reloadable performance counters
In accordance with embodiments disclosed herein, there is provided systems and methods for monitoring performance of a processor to manage events. A processor...
US-9,766,979 Error correction in solid state drives (SSD)
A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less...
US-9,766,971 Physical layer device operation system and method
Apparatuses, systems and methods associated with causing a physical layer (PHY) device are disclosed herein. In embodiments, an apparatus may include a memory...
US-9,766,968 Byte level granularity buffer overflow detection for memory corruption detection architectures
Memory corruption detection technologies are described. A processor can include a memory to store data from an application, wherein the memory comprises a...
US-9,766,963 Secure tunneling access to debug test ports on non-volatile memory storage units
Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug...
US-9,766,897 Method and apparatus for integral image computation instructions
A method is described that performing an image integral calculation by creating a second vector and creating a third vector. The second vector is created by...
US-9,766,893 Executing instruction sequence code blocks by using virtual cores instantiated by partitionable engines
A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a...
US-9,766,892 Method and apparatus for efficient execution of nested branches on a graphics processor unit
An apparatus and method for executing nested control flow instructions on a graphics processing unit (GPU). For example, one embodiment of a processor...
US-9,766,891 Apparatus, system, and method for persistent user-level thread
Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and...
US-9,766,889 Memory management in secure enclaves
Embodiments of an invention for memory management in secure enclaves are disclosed. In one embodiment, a processor includes an instruction unit and an execution...
US-9,766,888 Processor instruction to store indexes of source data elements in positions representing a sorted order of the...
A processor of an aspect includes packed data registers, and a decode unit to decode an instruction. The instruction may indicate a first source packed data to...
US-9,766,887 Multi-register gather instruction
A processor fetches a multi-register gather instruction that includes a destination operand that specifies a destination vector register, and a source operand...
US-9,766,886 Instruction and logic to provide vector linear interpolation functionality
Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a...
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