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Patent # Description
US-8,171,225 Cache for a multi thread and multi core system and methods thereof
A method includes storing a plurality of data RAM, holding information for all outstanding requests forwarded to a next-level memory subsystem, clearing...
US-8,171,223 Method and system to increase concurrency and control replication in a multi-core cache hierarchy
A directory of a private cache hierarchy is provided to maintain coherency between data stored in the cache hierarchy, where the directory is to enable...
US-8,171,219 Method and system to perform caching based on file-level heuristics
A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by...
US-8,171,205 Wrap-around sequence numbers for recovering from power-fall in non-volatile memory
Incrementing sequence numbers in the metadata of non-volatile memory is used in the event of a resume from power fail to determine which data in the memory is...
US-8,171,121 Method, system, and apparatus for dynamic reconfiguration of resources
A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system,...
US-8,171,095 Speculative distributed conflict resolution for a cache coherency protocol
A conflict resolution technique provides consistency such that all conflicts can be detected by at least one of the conflicting requestors if each node monitors...
US-8,170,859 Methods, apparatuses and computer program products for simulating arbitrary unmodified code
Arbitrary, unmodified code and/or software may be executed directly on a host processor operating in a virtualized mode using hardware virtualization support...
US-8,170,631 Folding electronic device with continuous display
In general, in one aspect, the disclosure describes an apparatus that includes two panels pivotally connected together. The panels can pivot from an open...
US-8,170,510 Minimizing mutual coupling
Disclosed herein are techniques, systems, and methods relating to minimizing mutual coupling between a first antenna and a second antenna.
US-8,170,488 Mitigation of internetwork interference
When a device in one wireless network receives interfering transmissions from an overlapping neighboring network, the neighboring network may be notified of the...
US-8,170,481 Techniques for discovering services provided in a wireless network
An embodiment of the present invention provides a method for discovering services provided in a wireless network, comprising enabling devices equipped with...
US-8,170,212 Device, system, and method of establishing secure wireless communication
Device, system, and method of establishing secure wireless communication. A system includes at least one wireless communication device having a sensor to...
US-8,170,062 Packetized interface for coupling agents
In one embodiment, the present invention includes a fabric on a first semiconductor die to communicate with at least one agent on the die according to an...
US-8,169,959 System aided PAPR reduction scheme based on TR algorithm
A peak-to-average power ratio (PAPR) reduction method, known as system-aided PAPR reduction (SAPR), is disclosed. Based on a TR algorithm, the SAPR method...
US-8,169,940 Techniques for device and piconet controller availability notification in wireless personal area and wireless...
An embodiment of the present invention provides a method, comprising notifying of device and piconet controller (PNC) availability in wireless personal area...
US-8,169,935 Multi-radio connection management and bundling using web browsers
A method to enable browsers to manage connections across access networks is disclosed. The method manages network connections using a simple standard browser...
US-8,169,925 Mapping of preamble sequence sets with frame control header (FCH) location for multi-hop wireless broadband...
FCH locations are mapped to preamble sequence sets to allow more than three stations to transmit their FCHs with minimized or reduced interference. A lower...
US-8,169,850 Forming multiprocessor systems using dual processors
In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled...
US-8,169,271 Interference resistant local oscillator
With some embodiments, a VCO (voltage controlled oscillator) operates at an integer multiple (N) above a desired transmission frequency. In accordance with one...
US-8,169,027 Substrate band gap engineered multi-gate pMOS devices
A multi-gate transistor and a method of forming a multi-gate transistor, the multi-gate transistor including a fin having an upper portion and a lower portion....
US-8,168,508 Method of isolating nanowires from a substrate
A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom...
US-8,168,488 Systems and methods for reducing contact to gate shorts
A method for reducing contact to gate shorts in a semiconductor device and the resulting semiconductor device are described. In one embodiment, a gate is formed...
US-8,166,471 Implementing portable content protection to secure secrets
A source-level compiler may randomly select compilation conventions to implement portable content protection, securing the secrets embedded in a program by...
US-8,166,325 Non main CPU/OS based operational environment
A computing system is described that includes a main system bus that remains active while said computing system operates within a non main CPU/OS based...
US-8,166,323 Thread migration to improve power efficiency in a parallel processing environment
A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one...
US-8,166,320 Power aware software pipelining for hardware accelerators
Forming a plurality of pipeline orderings, each pipeline ordering comprising one of a sequential, a parallel, or a sequential and parallel combination of a...
US-8,166,282 Multi-version register file for multithreading processors with live-in precomputation
Disclosed are selected embodiments of a processor that may include a plurality of thread units and a register file architecture to support speculative...
US-8,166,229 Apparatus and method for multi-level cache utilization
In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass...
US-8,166,223 Apparatuses to provide a message signaled interrupt to generate a PCI express interrupt
Machine-readable media, methods, and apparatus are described to issue message signaled interrupts. In some disclosed embodiments, a device generates message...
US-8,166,218 Memory buffers for merging local data from memory modules
An integrated circuit to serialize local data and selectively merge it with serialized feed-through data into a serial data stream output that includes a...
US-8,166,215 Method to control delay between lanes
Method and apparatus to control delay between lanes in an I/O interface is disclosed. To control the delay between the lanes in the I/O system a programmed...
US-8,166,207 Querying a device for information
In one embodiment, the present invention includes a method for receiving in a processor complex a first write request from a peripheral device, obtaining...
US-8,165,631 Sharing a radio frequency interface resource
Applications may seek access to a radio frequency interface resource on a processor-based system that exceeds the available capacity of that resource. When more...
US-8,165,428 Optical imaging based computer pointing
Methods and systems for optical imaging based computer pointing, including optical imaging based pointing motion and button functionality. Optical image motion...
US-8,165,241 Closed loop feedback in MIMO systems
Feedback bandwidth may be reduced in a closed loop MIMO system by factoring non essential information out of a beamforming matrix.
US-8,165,233 Multi-element antenna beamforming in a wireless access network
A communication node of a wireless local area network utilizes a multi-element array antenna to estimate an angle-of-arrival for one or more signal sources...
US-8,165,160 Method and system to validate a write for a device on a serial bus
A method and system, the method including, in some embodiments, calculating, by a message originator, a first check sum byte, appending the first check sum byte...
US-8,165,028 Monitoring in communication system with wireless trunk
A communication system having a wireless trunk for connecting multiple phone lines over wireless communication links to a cellular network comprises a central...
US-8,164,169 Cooling devices in semiconductor packages
An embodiment of the present invention is a technique to fabricate a cover assembly. A cover has a base plate and sidewalls attached to perimeter of the base...
US-8,163,830 Nanoclays in polymer compositions, articles containing same, processes of making same, and systems containing same
A composition includes a bismaleimide triazine (BT) compound with a nanoclay composited therewith. A mounting substrate includes polymer compound with a...
US-8,163,598 Clipless integrated heat spreader process and materials
In one or more embodiments, a method comprising applying thermo compression to a package assembly including a lid, a die, and a package substrate to assemble...
US-8,161,609 Methods of fabricating an array capacitor
Methods of fabricating an array capacitor are disclosed, in which via structures of the array capacitor have increased uniformity in their transverse areas. One...
US-8,161,564 Methods and apparatus for protecting digital content
A processing system to serve as a source device for protected digital content comprises a processor and control logic. When used by the processor, the control...
US-8,161,356 Systems, methods, and apparatuses to save memory self-refresh power
Embodiments of the invention are generally directed to systems, methods, and apparatuses to save dynamic random access memory (DRAM) self-refresh power. In some...
US-8,161,343 Nibble encoding for improved reliability of non-volatile memory
A wireless device to include a non-volatile memory to execute an encoding scheme to provide single-cell error detection and correction on program operations in...
US-8,161,322 Methods and apparatus to initiate a BIOS recovery
Methods and apparatus to initiate a basic input/output system (BIOS) recovery are disclosed herein. An example BIOS recovery module includes a memory storing...
US-8,161,299 Location based policy system and method for changing computing environments
A system and method for changing compute environments for a mobile platform device. The mobile platform includes a sensory and location determination engine...
US-8,161,280 Launching a secure kernel in a multiprocessor system
In one embodiment of the present invention, a method includes verifying a master processor of a system; validating a trusted agent with the master processor if...
US-8,161,269 Determining length of instruction with address form field exclusive of evaluating instruction specific opcode...
A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of...
US-8,161,258 Method to qualify access to a block storage device via augmentation of the device'S controller and firmware flow
A method to qualify access to a block storage device via augmentation of the device's controller and firmware flow. The method employs one or more block...
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