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Patent # Description
US-8,200,041 Hardware accelerated silhouette detection
Disclosed herein are approaches for detecting and/or generating silhouettes, in graphics processing applications, of objects (e.g., convex objects such as...
US-8,200,027 Methods and apparatus for retrieving images from a large collection of images
An image retrieval program (IRP) may be used to query a collection of digital images. The IRP may include a mining module to use local and global feature...
US-8,199,862 Arrangements for interference mitigation utilizing estimation
A method is disclosed for interference mitigation which can include receiving a signal having a data component, an interfering component and a time period and...
US-8,199,856 Arrangements for interference mitigation utilizing recursive estimation
A method is disclosed that includes receiving a signal having a data vector component and an interfering component and creating a first set of digitized data...
US-8,199,850 Transmitter for communication systems employing an enhanced modulation scheme
A transmitter is configured to transmit a transmit signal modulated according to a first modulation scheme, the first modulation scheme being associated with a...
US-8,199,809 Method and apparatus for providing prediction mode fine granularity scalability
In an encoding process, video data are represented as a bitstream of a quantized base layer and at least two enhancement layers, with each picture in each layer...
US-8,199,759 Method and apparatus for enabling ID based streams over PCI express
A method and apparatus for enabling ID based streams over Peripheral Component Interconnect Express (PCIe) is herein described. In this regard an apparatus is...
US-8,199,723 Parallel wireless communication apparatus, method, and system
An access point in a wireless network communicates with multiple mobile stations simultaneously using spatial-division multiple access. The access point...
US-8,199,158 Performance allocation method and apparatus
In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for...
US-8,198,965 Grounding of magnetic cores
An apparatus includes a magnetic core, a ground node, and one or more vias to provide a connection between the magnetic core and the ground potential. The...
US-8,198,929 Dynamic element matching for time-to-digital converters
Embodiments of the present disclosure provide methods, systems, and apparatuses related to dynamic element matching for time-to-digital converters. Other...
US-8,198,716 Die backside wire bond technology for single or stacked die package
Methods and apparatus to provide die backside connections are described. In one embodiment, the backside of a die is metallized and coupled to another die or a...
US-8,198,692 Spin torque magnetic integrated circuits and devices therefor
Spin torque magnetic integrated circuits and devices therefor are described. In an example, a spin torque magnetic device for a logic circuit includes a...
US-8,198,185 Apparatuses and methods to enhance passivation and ILD reliability
Some embodiments of the present invention include apparatuses and methods relating to processing and packaging microelectronic devices that reduce stresses on...
US-8,196,009 Systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared error bit...
Embodiments of the invention are generally directed to systems, methods, and apparatuses to transfer data and data mask bits in a common frame with a shared...
US-8,195,996 Apparatuses, systems and methods for detecting errors in data streams on point-to-point serial links
Methods, apparatuses and systems for physical link error data capture and analysis. A receiver is coupled to receive a data stream via a point-to-point serial...
US-8,195,968 System and method for power reduction by sequestering at least one device or partition in a platform from...
In some embodiments, the invention involves a system and method relating to managing power utilization in partitioned systems. In at least one embodiment, the...
US-8,195,914 Mechanism for remapping post virtual machine memory pages
According to one embodiment, a computer system is disclosed. The computer system includes a processor, a chipset coupled to the processor and a memory coupled...
US-8,195,898 Hybrid transactions for low-overhead speculative parallelization
A method and apparatus for a hybrid transactional memory system is herein described. A first transaction is executed utilizing a first style of a transactional...
US-8,195,891 Techniques to perform power fail-safe caching without atomic metadata
A method and system to allow power fail-safe write-back or write-through caching of data in a persistent storage device into one or more cache lines of a...
US-8,195,660 Method and apparatus to reorder search results in view of identified information of interest
Various embodiments described herein provide systems, methods, and software to automatically reorder search results presented to users based on information...
US-8,195,221 Loop delay compensation for continuous time sigma delta analog to digital converter
A continuous time sigma delta analog to digital converter may use a finite impulse response filter for delay compensation. In some embodiments, the filter may...
US-8,195,146 Remote management over a wireless wide-area network using short message service
A method and device for remote management over a wireless wide-area network includes receiving a short message over a wireless wide-area network (WWAN) using an...
US-8,195,001 In-loop adaptive wiener filter for video coding and decoding
A video encoder may use an adaptive Wiener filter inside the core video encoding loop to improve coding efficiency. In one embodiment, the Wiener filter may be...
US-8,194,854 Method and apparatus for optimizing advanced encryption standard (AES) encryption and decryption in parallel...
The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions)...
US-8,194,811 Clock repeater and phase-error correcting circuit
Embodiments of a clock repeater and phase-error correcting circuit are generally described herein. Other embodiments may be described and claimed. In some...
US-8,194,798 MIMO symbol decoder and method for decoding spatially multiplexed symbols using combined linear equalization...
Embodiments of MIMO symbol decoders and methods for decoding spatially multiplexed symbols using combined linear equalization decoding and maximum likelihood...
US-8,194,777 Apparatus and associated methods to perform space-frequency interleaving in a multicarrier wireless...
An apparatus and associated methods for performing space-frequency interleaving in a multicarrier wireless communication system is generally described.
US-8,194,769 GERAN transceiver and method for cooperative channel encoding across multiple GERAN tonal carriers
Embodiments of a GERAN transceiver for communicating in a global system for mobile communications (GSM) enhanced data rates for GSM evolution (EDGE) radio...
US-8,194,699 Radio scheduler and data plane interface
A media access control architecture operates to receive bandwidth requests in a first radio frame from mobile stations for uplink transmissions. A data plane...
US-8,194,687 Access point configured for station group management and method for managing station-management groups
Embodiments of an access point configured for station group management and a method for managing station-management groups in a wireless network are generally...
US-8,194,543 Methods of data traffic shaping, apparatus and wireless device
Methods of data traffic shaping, an apparatus and a wireless device are provided. A method of data traffic shaping comprises receiving data packets, the data...
US-8,194,448 Technique to reduce FG-FG interference in multi bit NAND flash memory in case of adjacent pages not fully...
A method of reducing floating gate-floating gate interference in programming NAND flash memory is provided. Prior to programming an upper page of a memory cell,...
US-8,194,244 Solution sample plate with wells designed for improved Raman scattering signal detection efficiency
Devices, methods of using the device, systems including the device that include a sample plate with sample containers (wells), wherein at least a portion of the...
US-8,193,994 Millimeter-wave chip-lens array antenna systems for wireless networks
Embodiments of chip-lens array antenna systems are described. In some embodiments, the chip-lens array antenna systems (100) may comprise a millimeter-wave lens...
US-8,193,858 Setting an output level of an amplifier apparatus
An amplifier module comprises an amplifier with an output and a coupling element for receiving a signal at the output. It also comprises a control input for...
US-8,193,641 Recessed workfunction metal in CMOS transistor gates
A transistor gate comprises a substrate having a pair of spacers disposed on a surface, a high-k dielectric conformally deposited on the substrate between the...
US-8,193,593 Multi-layer gate dielectric
A transistor gate dielectric including a first dielectric material having a first dielectric constant and a second dielectric material having a second...
US-8,193,567 Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
A process capable of integrating both planar and non-planar transistors onto a bulk semiconductor substrate, wherein the channel of all transistors is definable...
US-8,193,523 Germanium-based quantum well devices
A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close...
US-8,193,072 Semiconductor wafer coat layers and methods therefor
Formulations and processes for forming wafer coat layers are disclosed. In one embodiment, an organic surface protectant is incorporated into a wafer coat...
US-8,193,049 Methods of channel stress engineering and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion...
US-8,191,793 Method and system of advanced fan speed control
According to some embodiments, a method, system, and apparatus to provide thermal management control. In some embodiments, the method includes receiving, by a...
US-8,191,062 System for processor frequency governors to govern a processor frequency by deriving CPU utilization...
A method, apparatus and system enable processor frequency governors to comprehend virtualized platforms. Specifically, in one embodiment, the processor...
US-8,190,930 Methods and apparatuses for controlling thread contention
An apparatus comprises a plurality of cores and a controller coupled to the cores. The controller is to lower an operating point of a first core if a first...
US-8,190,870 Network storage target boot and network connectivity through a common network device
The present disclosure includes systems and techniques relating to booting to a network storage target. In general, in one implementation, a bus-to-network...
US-8,190,867 Packing two packed signed data in registers with saturation
A processor comprising a register file, and a decoder to decode an instruction to specify a first source register having a first packed signed 16-bit integers,...
US-8,190,863 Apparatus and method for heterogeneous chip multiprocessors via resource allocation and restriction
A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource...
US-8,190,859 Critical section detection and prediction mechanism for hardware lock elision
A method and apparatus for detecting lock instructions and lock release instruction, as well as predicting critical sections is herein described. A lock...
US-8,190,845 System and method for allocating and deallocating memory within transactional code
Methods and systems are provided for managing memory allocations and deallocations while in transactional code, including nested transactional code. The methods...
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