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Network packet payload compression
Methods and apparatus relating to network packet payload compression/decompression are described. In an embodiment, an uncompressed packet payload may be...
Canceling self-jammer and interfering signals in an RFID system
Briefly, in accordance with one or more embodiments, a method and device capable of canceling self-jammer and one or more other interfering signals in an radio...
Rail-to-rail data receiver for high-speed communication
In one embodiment, the present invention includes a receiver having two complementary input sense amplifiers to receive, amplify and latch a differential signal...
Buried dual taper waveguide for passive alignment and photonic integration
A buried dual taper waveguide has a flat surface after taper processing thus facilitating further processing with more complex photonic integrated circuits....
Fingerprint detecting wireless device
A wireless device, such as a remote control unit, may include an internal fingerprint identification unit. The fingerprint identification unit may be arranged...
De-activation, at least in part, of receiver, in response, at least in
part, to determination that an idle...
In one embodiment, a method is provided. In the method of this embodiment, in response, at least in part, to a determination that an idle condition exists, one...
Double-electrode cantilever actuation for seek-scan-probe data access
A seek-scan-probe memory device, utilizing a media electrode to allow active cantilevers to contact the storage media, and a pull electrode to pull up...
Optical modulator using a dual output laser embedded in a mach zehnder
A laser is placed inside the Mach-Zehnder interferometer and the output from opposite ends of the laser are fed directly into the opposite arms of the...
Displaying data on lower resolution displays
Data intended to be displayed on a higher resolution display such as a non-interlaced display used as a computer monitor may be converted for display on a lower...
Analyzing alpha values for flicker filtering
A flicker filter is adjusted according to degree of alpha blending performed on a display signal. For some weakly showing graphics images, a lower flicker...
Embedded assessment of refuse for activity monitoring
Embodiments of the present invention provide devices and methods for monitoring the waste output of one or more individuals. Embodiments provide a waste...
Power switches having positive-channel high dielectric constant insulated
gate field effect transistors
Power switch units for microelectronic devices are disclosed. In one aspect, a microelectronic device may include a functional circuit, and a power switch unit...
Digital phase locked loop with closed loop linearization technique
Apparatuses, systems, and a method for providing a digital phase-locked loop (PLL) are described. In one embodiment, an apparatus includes an integration-mode...
Phase memorization for low leakage dielectric films
Embodiments of a phase-stable amorphous high-.kappa. dielectric layer in a device and methods for forming the phase-stable amorphous high-.kappa. dielectric...
Embedded memory cell and method of manufacturing same
An embedded memory cell includes a semiconducting substrate (110), a transistor (120) having a source/drain region (121) at least partially embedded in the...
Low coefficient of thermal expansion (CTE) thermosetting resins for
integrated circuit applications
An embodiment of the present invention is a technique to form a resin. A mixture is formed by a curing agent dissolved in the epoxy resin. The epoxy resin...
Integrated circuit and process for fabricating thereof
A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further...
Heat dissipating device with preselected designed interface for thermal
Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is...
Method and apparatus for switching program streams using a variable speed
program stream buffer coupled to a...
Various embodiments for switching programs streams using a variable speed program stream buffer coupled to a variable speed decoder are described. In one or...
Streaming video programming guide system selecting video files from
multiple websites and automatically...
A programming guide for streaming video files may be automatically compiled in response to a user request. The user may provide keywords for categories of...
Method and system for a process monitor using a hardware communication
A method and system for a process monitor using a hardware communication format is described. The system includes a process monitor and a hardware device to...
Saving and restoring architectural state for processor cores
A method and apparatus for saving and restoring architectural states utilizing hardware is described. A first portion of an architectural state of a processing...
Attaching and virtualizing reconfigurable logic units to a processor
In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and...
Fair sharing of a cache in a multi-core/multi-threaded processor by
dynamically partitioning of the cache
An apparatus and method for fairly accessing a shared cache with multiple resources, such as multiple cores, multiple threads, or both are herein described. A...
Method and apparatus for reducing memory latency in a cache coherent
A method for reducing memory latency in a multi-node architecture. In one embodiment, a speculative read request is issued to a home node before results of a...
K-way direct mapped cache
A method and apparatus for a k-way direct mapped cache organization is herein described. Control logic coupled to a cache may associate an address to a way...
Multithreaded clustered microarchitecture with dynamic back-end assignment
A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and...
Multi-node chipset lock flow with peer-to-peer non-posted I/O requests
Systems and methods of managing transactions provide for receiving a first flush command at a first I/O hub, wherein the first flush command is dedicated to...
Message communication techniques
A network protocol unit interface is described that uses a message engine to transfer contents of received network protocol units in message segments to a...
Virtual clustering for scalable network control and management
In some embodiments, the invention involves a system and method relating to a framework to build a new class of network control (policy) and (state) management...
Remote unit for providing spatial processing
Methods and apparatus implementing spatial processing in a remote unit. In general, in one aspect, a remote unit in accordance with the invention includes a...
CQI reporting techniques for OFDMA wireless networks
Various embodiments of the invention may use bitmaps to communicate channel quality index (CQI) information for multiple sub-channels in an orthogonal frequency...
Method and system of secured direct link set-up (DLS) for wireless
Method and system of secured direct link set-up (DLS) for wireless networks. In accordance with aspects of the method, techniques are disclosed for setting up...
High-performance WiMAX QoS condition scheduling mechanism
Embodiments of a method and apparatus for a high performance worldwide interoperability for microwave access quality of service condition scheduling mechanism...
A method, apparatus, and signal-bearing medium for sending to a display device only those regions of the display screen that change. A frame buffer is divided...
Device and method for particle complex handling
An embodiment of the invention relates to a device for detecting an analyte in a sample. The device comprises a fluidic network and an integrated circuitry...
Methods and apparatuses for core allocations
Apparatuses, systems, and methods to monitor core performance and integrated circuit chip temperatures in order to alternatively partition cores and core...
Processor control register virtualization to minimize virtual machine
A processor includes a processor control register with a control flag that determines an operating mode of the processor. A pointer to a guest virtual machine...
Arrangements for encoding and decoding digital data
A method for encoding data is disclosed. The method can include receiving a first bit segment (K-1 bits) from a bit stream, storing the first bit segment,...
Failover and load balancing
Provided are techniques for static load balancing implemented in a filter driver. The filter driver determines a data quota for each of multiple data paths. The...
Firewall/isolation cells for ultra low power products
In an integrated circuit (IC) may have several functional blocks adapted to be inactivated independently from each other. At least one firewall cell may be...
Methods and apparatuses for reducing step loads of processors
Methods and apparatuses for reducing step loads of processors are disclosed. Method embodiments comprise examining a number of instructions to be processed by a...
Power reduction for system on chip
Disclosed herein are SOC devices with peripheral units having power management logic.
Comparing text strings
A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be...
Register set used in multithreaded parallel processor architecture
A parallel hardware-based multithreaded processor. The processor includes a general purpose processor that coordinates system functions and a plurality of...
Efficient usage of last level caches in a MCMP system using application
This disclosure presents an architectural mechanism which allows a caching bridge to efficiently store data either inclusively or exclusively based upon...
Technique for using memory attributes
A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory...
A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies. More particularly, embodiments of the...
In-memory, in-page directory cache coherency scheme
In an embodiment, the method provides receiving a memory access request for a demanded cache line from a processor of a plurality of processors; accessing...
Providing application-level information for use in cache management
In one embodiment, the present invention includes a method for associating a first identifier with data stored by a first agent in a cache line of a cache to...